Amd Geode LX [email protected] Uživatelský manuál Strana 1

Procházejte online nebo si stáhněte Uživatelský manuál pro Hardware Amd Geode LX [email protected]. AMD Geode LX [email protected] User Manual Uživatelská příručka

  • Stažení
  • Přidat do mých příruček
  • Tisk
  • Strana
    / 680
  • Tabulka s obsahem
  • KNIHY
  • Hodnocené. / 5. Na základě hodnocení zákazníků
Zobrazit stránku 0
AMD Geode™ LX Processors Data Book
AMD Geode™ LX Processors
Data Book
February 2009
Publication ID: 33234H
Zobrazit stránku 0
1 2 3 4 5 6 ... 679 680

Shrnutí obsahu

Strany 1 - Data Book

AMD Geode™ LX Processors Data Book AMD Geode™ LX Processors Data BookFebruary 2009Publication ID: 33234H

Strany 2

10 AMD Geode™ LX Processors Data Book - List of Tables33234HTable 8-12. sreg3 Field (FS and GS Segment Register Selection) . . . . . . . . . . . . .

Strany 3 - Contents

100 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H00001110h RO IF Sequential Count MRS (IF_SEQCOUNT_MSR) 00000000_00000000h P

Strany 4

AMD Geode™ LX Processors Data Book 101CPU Core Register Descriptions 33234H00001335h R/W GS Segment Base/Limit MSR (GS_BASE_MSR) xxxxxxxx_xxxxxxxxh P

Strany 5 - List of Figures

102 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H00001374h R/W Floating Point Environment Opcode Pointer (FPENV_OP_MSR)00000

Strany 6

AMD Geode™ LX Processors Data Book 103CPU Core Register Descriptions 33234H00001722h R/W ITB Entry MSR (ITB_ENTRY_MSR) xxxxxxxx_xxxxxxxxh Page 157000

Strany 7

104 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H00001813h R/W Region Configuration Range 3 MSR (RCONF3_MSR)00000000_0000000

Strany 8

AMD Geode™ LX Processors Data Book 105CPU Core Register Descriptions 33234H00001901h R/W Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR)00000000_

Strany 9

106 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H00001A03h R/W FPU Reserved MSR (FPU_RSVD_MSR) 00000000_00000000h Page 20200

Strany 10 - List of Tables

AMD Geode™ LX Processors Data Book 107CPU Core Register Descriptions 33234H00003000h R/W Standard Levels and Vendor ID String 1 (CPUID0_MSR)68747541_

Strany 11 - 1.0Overview

108 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.1 Standard GeodeLink™ Device MSRs5.5.1.1 GLD Capabilities MSR (GLD_MSR_

Strany 12 - 1.2 Features

AMD Geode™ LX Processors Data Book 109CPU Core Register Descriptions 33234H5.5.1.3 GLD SMI MSR (GLD_MSR_SMI)This register is not used in the CPU Core

Strany 13

AMD Geode™ LX Processors Data Book 111Overview 33234H1.0Overview1.1 General DescriptionAMD Geode™ LX processors are integrated x86 proces-sors specif

Strany 14 - Overview

110 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2 CPU Core Specific MSRs5.5.2.1 Time Stamp Counter MSR (TSC_MSR) 5.5.2.

Strany 15 - 2.0Architecture Overview

AMD Geode™ LX Processors Data Book 111CPU Core Register Descriptions 33234H5.5.2.3 Performance Event Counter 1 MSR (PERF_CNT1_MSR) MSR Address 000000

Strany 16 - 2.1.4 Bus Controller Unit

112 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.4 SYSENTER/SYSEXIT Code Segment Selector MSR (SYS_CS_MSR)SYS_CS_MSR i

Strany 17 - 2.5 Graphics Processor

AMD Geode™ LX Processors Data Book 113CPU Core Register Descriptions 33234H5.5.2.5 SYSENTER/SYSEXIT Stack Pointer MSR (SYS_SP_MSR)SYS_SP MSR is used

Strany 18 - 2.9 GeodeLink™ PCI Bridge

114 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.7 Performance Event Counter 0 Select MSR (PERF_SEL0_MSR 5.5.2.8 Perfo

Strany 19 - 2.10 Security Block

AMD Geode™ LX Processors Data Book 115CPU Core Register Descriptions 33234H5.5.2.9 Instruction Fetch Configuration MSR (IF_CONFIG_MSR)IF_CONFG_MSR co

Strany 20 - Architecture Overview

116 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H28 II_NS Instruction Pipeline (IP) Empty Mode. 0: IM Interface may make req

Strany 21 - 3.0Signal Definitions

AMD Geode™ LX Processors Data Book 117CPU Core Register Descriptions 33234H6STRONG Strong Prediction. Allow the IF to make strong predictions.0: Disa

Strany 22

118 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.10 IF Invalidate MSR (IF_INVALIDATE_MSR)IF_INVALIDATE MSR may be used

Strany 23 - 3.1 Buffer Types

AMD Geode™ LX Processors Data Book 119CPU Core Register Descriptions 33234H5.5.2.12 IF Test Data MSR (IF_TEST_DATA_MSR) 12:8 BLOCK Block Identifier.

Strany 24 - 3.3 Ball Assignments

12 AMD Geode™ LX Processors Data Book Overview33234H1.2 FeaturesGeneral Features Functional blocks include:—CPU Core— GeodeLink™ Control Processor— G

Strany 25 - LX Processor

120 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234HIF_TEST_DATA_MSR Register Map for Tag RAMs63 62 61 60 59 58 57 56 55 54 53

Strany 26 - Signal Definitions

AMD Geode™ LX Processors Data Book 121CPU Core Register Descriptions 33234HIF_TEST_DATA_MSR Register Map for Level-0 COF Cache Address63 62 61 60 59

Strany 27

122 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.13 IF Sequential Count MRS (IF_SEQCOUNT_MSR)IF SEQCOUNT MSR is a read

Strany 28

AMD Geode™ LX Processors Data Book 123CPU Core Register Descriptions 33234H5.5.2.14 IF Built-In Self-Test MSR (IF_BIST_MSR)IF_BIST_MSR may be used to

Strany 29

124 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.15 Exception Unit (XC) Configuration MSR (XC_CONFIG_MSR)XC_CONFIG_MSR

Strany 30

AMD Geode™ LX Processors Data Book 125CPU Core Register Descriptions 33234H5.5.2.16 XC Mode MSR (XC_MODE_MSR)XC_MODE_MSR contains information about t

Strany 31

126 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.17 XC History MSR (XC_HIST_MSR)MSR Address 00001212h Typ e ROReset Va

Strany 32

AMD Geode™ LX Processors Data Book 127CPU Core Register Descriptions 33234H5.5.2.18 XC Microcode Address MSR (XC_UADDR_MSR)5.5.2.19 ID Configuration

Strany 33 - 3.4 Signal Descriptions

128 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.20 SMM Control MSR (SMM_CTL_MSR)MSR Address 00001301hTyp e R /WReset

Strany 34 - 3.4.2 PLL Interface Signals

AMD Geode™ LX Processors Data Book 129CPU Core Register Descriptions 33234H5.5.2.21 Debug Management Interrupt (DMI) Control Register MSR Address 000

Strany 35

AMD Geode™ LX Processors Data Book 13Overview 33234HDisplay Controller Hardware frame buffer compression improves Unified Memory Architecture (UMA)

Strany 36

130 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.22 Temporary MSRsTemporary 0 MSR (TEMP0_MSR) Temporary 1 MSR (TEMP1_M

Strany 37 - 3.4.5 PCI Interface Signals

AMD Geode™ LX Processors Data Book 131CPU Core Register Descriptions 33234H5.5.2.23 Segment Selector/Flags MSRsThe Segment Selector/Flags MSRs provid

Strany 38

132 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.24 SMM Header MSR (SMM_HDR_MSR)The SMM_HDR_MSR provides access to the

Strany 39

AMD Geode™ LX Processors Data Book 133CPU Core Register Descriptions 33234H5.5.2.25 DMM Header MSR (DMM_HDR_MSR) DMM_HDR_MSR provides access to the a

Strany 40

134 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.26 Segment Base/Limit MSRsThe segment base/limit MSRs provide access

Strany 41 - 3.4.8 VIP Interface Signals

AMD Geode™ LX Processors Data Book 135CPU Core Register Descriptions 33234H5.5.2.27 Debug Registers 1 and 0 MSR (DR1_DR0_MSR) DR1_DR0_MSR provides ac

Strany 42

136 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.29 Debug Registers 7 and 6 MSR (DR6_DR7_MSR)DR7_DR6_MSR provides acce

Strany 43

AMD Geode™ LX Processors Data Book 137CPU Core Register Descriptions 33234H5.5.2.30 Extended Debug Registers 1 and 0 MSR (XDR1_XDR0_MSR) XDR1/XDR0_MS

Strany 44

138 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.32 Extended Debug Registers 5 and 4 MSR (XDR5_XDR4_MSR) XDR5/XDR4_MSR

Strany 45 - 4.0GeodeLink™ Interface Unit

AMD Geode™ LX Processors Data Book 139CPU Core Register Descriptions 33234HXDR7_XDR6_MSR Bit DescriptionsBit Name Description63:62 LEN3 Extended Brea

Strany 46 - 4.1.1 Port Address

14 AMD Geode™ LX Processors Data Book Overview33234H

Strany 47 - Table 4-2. MSR Mapping

140 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.34 Extended Debug Registers 9 and 8 MSR (XDR9_XDR8_MSR) XDR9_XDR8_MSR

Strany 48

AMD Geode™ LX Processors Data Book 141CPU Core Register Descriptions 33234H5.5.2.35 Extended Debug Registers 11 and 10 MSR (XDR11_XDR10_MSR) XDR11_XD

Strany 49

142 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.37 WB Stage Instruction Pointer MSR (WB_IP_MSR) WB_IP_MSR provides ac

Strany 50 - P2D Descriptor

AMD Geode™ LX Processors Data Book 143CPU Core Register Descriptions 33234H5.5.2.39 WB Stage Linear Instruction Pointer MSR (WB_LIP_MSR) WB_LIP_MSR p

Strany 51 - GLIU Register Descriptions

144 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.41 C3/C2 Linear Instruction Pointer MSR (C3_C2_LIP_MSR) C3_C2_LIP_MSR

Strany 52

AMD Geode™ LX Processors Data Book 145CPU Core Register Descriptions 33234H5.5.2.43 Floating Point Environment Instruction Pointer (FPENV_IP_MSR)FPEN

Strany 53

146 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.45 Floating Point Environment Data Pointer (FPENV_DP_MSR)FPENV_DP_MSR

Strany 54

AMD Geode™ LX Processors Data Book 147CPU Core Register Descriptions 33234H5.5.2.47 Address Calculation Unit Configuration MSR (AC_CONFIG_MSR) MSR Ad

Strany 55 - _MSR_CONFIG Bit Descriptions

148 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.48 General Register MSRsGeneral Register EAX MSR (GR_EAX_MSR) General

Strany 56 - _MSR_SMI Bit Descriptions

AMD Geode™ LX Processors Data Book 149CPU Core Register Descriptions 33234H5.5.2.49 Extended Flags MSR (EFLAG_MSR)5.5.2.50 Control Register 0 MSR (CR

Strany 57 - _MSR_ERROR Bit Descriptions

AMD Geode™ LX Processors Data Book 152Architecture Overview 33234H2.0Architecture OverviewThe CPU Core provides maximum compatibility with thevast am

Strany 58

150 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.51 Instruction Memory Configuration MSR (IM_CONFIG_MSR)MSR Address 00

Strany 59 - _MSR_PM Register Map

AMD Geode™ LX Processors Data Book 151CPU Core Register Descriptions 33234H8ICD Instruction Cache Disable. Completely disable L0 and L1 instruction c

Strany 60 - COH Bit Descriptions

152 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.52 Instruction Cache Index MSR (IC_INDEX_MSR)5.5.2.53 Instruction Cac

Strany 61 - PAE Bit Descriptions

AMD Geode™ LX Processors Data Book 153CPU Core Register Descriptions 33234H5.5.2.54 Instruction Cache Tag (IC_TAG_MSR)MSR Address 00001712h Typ e R /

Strany 62 - ASMI Register Map

154 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.55 Instruction Cache Tag with Increment (IC_TAG_I_MSR)5.5.2.56 L0 Ins

Strany 63 - ASMI Bit Descriptions

AMD Geode™ LX Processors Data Book 155CPU Core Register Descriptions 33234H5.5.2.58 L1 Instruction TLB Index (ITB_INDEX_MSR)The L1 Instruction TLB is

Strany 64 - AERR Bit Descriptions

156 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.59 L1 Instruction TLB Least Recently Used MSR (ITB_LRU_MSR)MSR Addres

Strany 65 - PHY_CAP Bit Descriptions

AMD Geode™ LX Processors Data Book 157CPU Core Register Descriptions 33234H5.5.2.60 L1 Instruction TLB Entry MSRsITB Entry MSR (ITB_ENTRY_MSR)ITB Ent

Strany 66 - NOUT_RESP Bit Descriptions

158 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.61 Instruction Memory Subsystem BIST Tag MSR (IM_BIST_TAG_MSR)The Ins

Strany 67 - SLAVE_ONLY Bit Descriptions

AMD Geode™ LX Processors Data Book 159CPU Core Register Descriptions 33234H5.5.2.63 Data Memory Subsystem Configuration 0 MSR (DM_CONFIG0_MSR)MSR Add

Strany 68 - WHO AM I Bit Descriptions

16 AMD Geode™ LX Processors Data Book Architecture Overview33234H2.1.2 Memory Management UnitThe memory management unit (MMU) translates the linearadd

Strany 69 - GLIU_SLV Bit Descriptions

160 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H32 WBDIS Write Buffer Disable. Disabling the write buffer forces stores to

Strany 70 - ARB2 Bit Descriptions

AMD Geode™ LX Processors Data Book 161CPU Core Register Descriptions 33234H7 SPCDEC Decrease Number of Speculative Reads of Data Cache. 0: Actively r

Strany 71

162 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.64 Data Memory Subsystem Configuration 1 MSR (DM_CONFIG1_MSR)MSR Addr

Strany 72

AMD Geode™ LX Processors Data Book 163CPU Core Register Descriptions 33234H5.5.2.65 Data Memory Subsystem Prefetch Lock MSR (DM_PFLOCK_MSR)20 NOPFXEV

Strany 73

164 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.66 Default Region Configuration Properties MSR (RCONF_DEFAULT_MSR)DM_

Strany 74 - RQ_COMPARE_VAL[0:3] Register

AMD Geode™ LX Processors Data Book 165CPU Core Register Descriptions 33234H5.5.2.67 Region Configuration Bypass MSR (RCONF_BYPASS_MSR) 5.5.2.68 Regio

Strany 75

166 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.69 Region Configuration C0000-DFFFF MSR (RCONF_C0_DF_MSR) 5.5.2.70 Re

Strany 76

AMD Geode™ LX Processors Data Book 167CPU Core Register Descriptions 33234H5.5.2.71 Region Configuration SMM MSR (RCONF_SMM_MSR) RCONF_E0_FF_MSR Bit

Strany 77

168 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.72 Region Configuration DMM MSR (RCONF_DMM_MSR) MSR Address 0000180Fh

Strany 78

AMD Geode™ LX Processors Data Book 169CPU Core Register Descriptions 33234H5.5.2.73 Region Configuration Range MSRs 0 through 7Region Configuration R

Strany 79 - DA_COMPARE_MASK_HI[0:3])

AMD Geode™ LX Processors Data Book 17Architecture Overview 33234H2.5 Graphics ProcessorThe Graphics Processor is based on the graphics proces-sor use

Strany 80 - P2D_BM Bit Descriptions

170 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234HRegion PropertiesThe region properties consist of an 8-bit field as shown i

Strany 81 - P2D_BMO Bit Descriptions

AMD Geode™ LX Processors Data Book 171CPU Core Register Descriptions 33234HIf paging is enabled, the region properties can be further modified by the

Strany 82 - P2D_R Bit Descriptions

172 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.74 x86 Control Registers MSRs (CR1, CR2, CR3, CR4)These are the stand

Strany 83 - P2D_RO Bit Descriptions

AMD Geode™ LX Processors Data Book 173CPU Core Register Descriptions 33234H5.5.2.76 Data Cache Data MSR (DC_DATA_MSR)5.5.2.77 Data Cache Tag MSR (DC_

Strany 84 - P2D_SC Bit Descriptions

174 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.78 Data Cache Tag with Increment MSR (DC_TAG_I_MSR)Bit descriptions f

Strany 85 - SPARE_MSR[x] Bit Descriptions

AMD Geode™ LX Processors Data Book 175CPU Core Register Descriptions 33234H5.5.2.79 Data/Instruction Cache Snoop Register (SNOOP_MSR)The SNOOP_MSR pr

Strany 86 - IOD_BM[x] Bit Descriptions

176 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.81 L1 Data TLB Least Recently Used MSR (L1DTLB_LRU_MSR) MSR Address 0

Strany 87 - IOD_SC[x] Bit Descriptions

AMD Geode™ LX Processors Data Book 177CPU Core Register Descriptions 33234H5.5.2.82 L1 Data TLB Entry MSR (L1DTLB_ENTRY_MSR) MSR Address 0000189AhTyp

Strany 88

178 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.83 L1 Data TLB Entry with Increment MSR (L1DTLB_ENTRY_I_MSR) Bit desc

Strany 89 - 5.0CPU Core

AMD Geode™ LX Processors Data Book 179CPU Core Register Descriptions 33234H5.5.2.85 L2 TLB/DTE/PTE Least Recently Used MSR (L2TLB_LRU_MSR)15:6 RSVD (

Strany 90 - 5.2 Instruction Set Overview

18 AMD Geode™ LX Processors Data Book Architecture Overview33234H2.6 Display ControllerThe Display Controller performs the following functions:1) Retr

Strany 91 - 5.3 Application Register Set

180 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.86 L2 TLB/DTE/PTE Entry MSR (L2TLB_ENTRY_MSR) 21:16 PTE_LRU 4M PTE Le

Strany 92 - 5.3.2 Segment Registers

AMD Geode™ LX Processors Data Book 181CPU Core Register Descriptions 33234H7 RSVD (RO) Reserved (Read Only). 6DIRTY Dirty Flag. A 1 indicates that th

Strany 93 - Table 5-4. EFLAGS Register

182 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.87 L2 TLB/DTE/PTE Entry with Increment MSR (L2TLB_ENTRY_I_MSR) Bit de

Strany 94 - 5.4 System Register Set

AMD Geode™ LX Processors Data Book 183CPU Core Register Descriptions 33234H5.5.2.89 Bus Controller Configuration 0 MSR (BC_CONFIG0_MSR) 5 RETEN_TLB L

Strany 95 - 5.4.1 Control Registers

184 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.90 Bus Controller Configuration 1 MSR (BC_CONFIG1_MSR) This register

Strany 96 - CPU Core

AMD Geode™ LX Processors Data Book 185CPU Core Register Descriptions 33234H5.5.2.91 Reserved Status MSR (RSVD_STS_MSR) 5.5.2.92 MSR Lock MSR (MSR_LO

Strany 97

186 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.93 Real Time Stamp Counter MSR (RTSC_MSR) 5.5.2.94 TSC and RTSC Low D

Strany 98

AMD Geode™ LX Processors Data Book 187CPU Core Register Descriptions 33234H5.5.2.95 L2 Cache Configuration MSR (L2_CONFIG_MSR)L2_CONFIG_MSR controls

Strany 99

188 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.96 L2 Cache Status MSR (L2_STATUS_MSR)L2_STATUS_MSR returns the statu

Strany 100

AMD Geode™ LX Processors Data Book 189CPU Core Register Descriptions 33234H5.5.2.98 L2 Cache Data MSR (L2_DATA_MSR) L2_DATA_MSR is used to access the

Strany 101

AMD Geode™ LX Processors Data Book 19Architecture Overview 33234H2.10 Security BlockThe AMD Geode LX processor has an on-chip AES 128-bitcrypto accel

Strany 102

190 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.100 L2 Cache Tag with Increment MSR (L2_TAG_I_MSR)The L2_TAG_I_MSR h

Strany 103

AMD Geode™ LX Processors Data Book 191CPU Core Register Descriptions 33234H10 BIST_TAG_GO_WAY3 (RO)L2 Cache Tag BIST Way 3 Result (Read Only).0: Fail

Strany 104

192 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.102 L2 Cache Treatment Control MSR (L2_TRTMNT_CTL_MSR)MSR Address 000

Strany 105

AMD Geode™ LX Processors Data Book 193CPU Core Register Descriptions 33234H5.5.2.103 Power Mode MSR (PMODE_MSR)This MSR enables some modules to turn

Strany 106

194 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.104 Bus Controller Extended Debug Registers 1 and 0 MSR (BXDR1_BXDR0_

Strany 107

AMD Geode™ LX Processors Data Book 195CPU Core Register Descriptions 33234H5.5.2.106 Bus Controller Extended Debug Registers 6 and 7 MSR (BXDR6_BXDR7

Strany 108 - GLD_MSR_CONFIG Register Map

196 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H41:40 LEN0 Extended Breakpoint 0 Length. Selects the size of extended break

Strany 109

AMD Geode™ LX Processors Data Book 197CPU Core Register Descriptions 33234H5.5.2.107 Bus Controller Debug Registers 0 through 3 MSRsEach of these reg

Strany 110 - TSC_MSR Register Map

198 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.108 Bus Controller Debug Register 6 MSR (BDR6_MSR)This register conta

Strany 111 - PERF_CNT1_MSR Register Map

AMD Geode™ LX Processors Data Book 199CPU Core Register Descriptions 33234H31:28 TYPE3 Breakpoint 3 Type. Selects the type of extended breakpoint 3.

Strany 112 - SYS_CS_MSR Bit Descriptions

2 AMD Geode™ LX Processors Data Book © 2009 Advanced Micro Devices, Inc. All rights reserved.The contents of this document are provided in connection

Strany 113 - SYS_IP_MSR Bit Descriptions

20 AMD Geode™ LX Processors Data Book Architecture Overview33234H

Strany 114 - PERF_SEL1_MSR Register Map

200 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.110 Memory Subsystem Array Control Enable MSR (MSS_ARRAY_CTL_EN_MSR)

Strany 115 - IF_CONFIG_MSR Register Map

AMD Geode™ LX Processors Data Book 201CPU Core Register Descriptions 33234H5.5.2.112 Memory Subsystem Array Control 1 MSR (MSS_ARRAY_CTL1_MSR)5.5.2.1

Strany 116

202 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.114 FPU Modes MSR (FP_MODE_MSR) 5.5.2.115 FPU Reserved MSR (FPU_RSVD_

Strany 117

AMD Geode™ LX Processors Data Book 203CPU Core Register Descriptions 33234H5.5.2.117 FPU x87 Control Word MSR (FPU_CW_MSR) 5.5.2.118 FPU x87 Status W

Strany 118 - IF_TEST_ADDR_MSR Register Map

204 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.120 FPU Busy MSR (FPU_BUSY_MSR) 5.5.2.121 FPU Register Map MSR (FPU_M

Strany 119

AMD Geode™ LX Processors Data Book 205CPU Core Register Descriptions 33234H5.5.2.122 Mantissa of Rx MSRsMantissa of R0 MSR (FPU_MR0_MSR) Mantissa of

Strany 120

206 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234H5.5.2.123 Exponent of Rx MSRsExponent of R0 MSR (FPU_ER0_MSR) Exponent of R

Strany 121

AMD Geode™ LX Processors Data Book 207CPU Core Register Descriptions 33234H5.5.2.124 FPU Reserved MSRs (FPU_RSVD_MSR)MSR addresses 00001A60h through

Strany 122 - IF_SEQCOUNT_MSR Register Map

208 AMD Geode™ LX Processors Data Book CPU Core Register Descriptions33234HCPUIDx_MSR Register Map63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 4

Strany 123 - IF_BIST_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 2096Integrated Functions 33234H6.0Integrated FunctionsThe integrated functions of the AMD Geode™ LX proces-sor are

Strany 124 - XC_CONFIG_MSR Register Map

AMD Geode™ LX Processors Data Book 213Signal Definitions 33234H3.0Signal DefinitionsThis chapter defines the signals and describes the external inter

Strany 125 - XC_MODE_MSR Bit Descriptions

210 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller33234H6.1 GeodeLink™ Memory ControllerThe GeodeLink™ Memory Controller (GLMC) modul

Strany 126 - XC_HIST_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 211GeodeLink™ Memory Controller 33234HFeatures• Supports up to 400 MT/S (million transfers per second) DDR SDRAMs•

Strany 127 - ID_CONFIG_MSR Register Map

212 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller33234HAuto Low Order InterleavingThe GLMC requires that module banks [0:1], if both

Strany 128 - SMM_CTL_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 213GeodeLink™ Memory Controller 33234HTable 6-1. LOI - 2 DIMMs, Same Size, 1 DIMM Bank1 KB Page Size 2 KB Page Siz

Strany 129 - DMI Control Register Map

214 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller33234HTable 6-3. Non-Auto LOI - 1 or 2 DIMMs, Different Sizes, 1 DIMM Bank1 KB Page

Strany 130 - TEMPx_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 215GeodeLink™ Memory Controller 33234H6.1.1.2 ArbitrationThe pipelining of the GLMC module requests consists ofthe

Strany 131

216 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller33234H6.1.1.3 Data PathThe write datapath utilizes three write buffers to gatherwri

Strany 132 - SMM_HDR_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 217GeodeLink™ Memory Controller 33234HFigure 6-9. DDR Writesmph1m_sd_datadrdyrxrqin_readydainrqin_takewrx0wrx1wrx2

Strany 133 - DMM_HDR_MSR Bit Descriptions

218 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller33234H6.1.2 Power ControlThe GLMC employs some methods of power control forpower sa

Strany 134

AMD Geode™ LX Processors Data Book 219GeodeLink™ Memory Controller Register Descriptions 33234H6.2 GeodeLink™ Memory Controller Register Descriptions

Strany 135 - DR2_DR3_MSR Bit Descriptions

22 AMD Geode™ LX Processors Data Book Signal Definitions33234HTable 3-1. Video Signal Definitions Per ModeSignal Name CRT w/16-bit VIPRGB w/16-bit VIP

Strany 136 - DR7_DR6_MSR Bit Descriptions

220 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.1 Standard GeodeLink™ Device (GLD) MSRs6.2.1.1 GLD

Strany 137 - XDR3_XDR2_MSR Register Map

AMD Geode™ LX Processors Data Book 221GeodeLink™ Memory Controller Register Descriptions 33234H6.2.1.4 GLD Error MSR (GLD_MSR_ERROR)MSR Address 20002

Strany 138 - XDR7_XDR6_MSR Register Map

222 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.1.5 GLD Power Management (GLD_MSR_PM)6.2.1.6 GLD Di

Strany 139

AMD Geode™ LX Processors Data Book 223GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2 GLMC Specific MSRs6.2.2.1 Row Addresses Bank0 DI

Strany 140 - XDR9_XDR8_MSR Register Map

224 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.2.3 Row Addresses Bank4 DIMM0, Bank5 DIMM0 (MC_CF_B

Strany 141 - EX_IP_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 225GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.5 Row Addresses Bank0 DIMM1, Bank1 DIMM0 (MC_CF_

Strany 142 - EX_LIP_MSR Bit Descriptions

226 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.2.7 Row Addresses Bank4 DIMM1, Bank5 DIMM1 (MC_CF_B

Strany 143 - C1_C0_LIP_MSR Register Map

AMD Geode™ LX Processors Data Book 227GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.9 Refresh and SDRAM Program (MC_CF07_DATA)MSR Ad

Strany 144 - FPENV_CS_MSR Bit Descriptions

228 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H36 D0_CB DIMM0 Component Banks. Number of component ban

Strany 145 - FPENV_DS_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 229GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.10 Timing and Mode Program (MC_CF8F_DATA)2 RSVD

Strany 146 - FPENV_OP_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 23Signal Definitions 33234H3.1 Buffer TypesThe Ball Assignment tables starting on page 26 include acolumn labeled

Strany 147 - AC_CONFIG_MSR Register Map

230 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234HMC_CF8F_DATA Bit DescriptionsBit Name Description63:56

Strany 148

AMD Geode™ LX Processors Data Book 231GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.11 Feature Enables (MC_CF1017_DATA)11:8 ACT2ACT

Strany 149 - EFLAG_MSR Bit Descriptions

232 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.2.12 Performance Counters (MC_CFPERF_CNT1)2:0 WR2DA

Strany 150 - IM_CONFIG_MSR Register Map

AMD Geode™ LX Processors Data Book 233GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.13 Counter and CAS Control (MC_PERCNT2)6.2.2.14

Strany 151

234 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234HMC_CFCLK_DBUG Bit DescriptionsBit Name Description63:35

Strany 152 - IC_DATA_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 235GeodeLink™ Memory Controller Register Descriptions 33234H6.2.2.15 Page Open Status (MC_CFPG_OPEN)6.2.2.16 Reser

Strany 153 - IC_TAG_MSR Bit Descriptions

236 AMD Geode™ LX Processors Data Book GeodeLink™ Memory Controller Register Descriptions33234H6.2.2.17 PM Sensitivity Counters (MC_CF_PMCTR)MSR Addre

Strany 154 - L0_IC_TAG_I_MSR Register Map

AMD Geode™ LX Processors Data Book 237Graphics Processor 33234H6.3 Graphics ProcessorThe Graphics Processor is based on the graphics proces-sor used

Strany 155 - ITB_INDEX_MSR Register Map

238 AMD Geode™ LX Processors Data Book Graphics Processor33234HTable 6-7. Graphics Processor Feature ComparisonFeature AMD Geode™ GX Processor AMD Geo

Strany 156 - ITB_LRU_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 239Graphics Processor 33234H6.3.1 Command BufferThe AMD Geode LX processor supports a command bufferinterface in a

Strany 157

24 AMD Geode™ LX Processors Data Book Signal Definitions33234H3.2 Bootstrap OptionsThe bootstrap options shown in Table 3-3 are supported inthe AMD Ge

Strany 158 - IM_BIST_DATA_MSR Register Map

240 AMD Geode™ LX Processors Data Book Graphics Processor33234HTable 6-9. Vector Command Buffer Structure31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

Strany 159 - DM_CONFIG0_MSR Register Map

AMD Geode™ LX Processors Data Book 241Graphics Processor 33234HWhere:6.3.2 Channel 3Channel 3 is an additional DMA channel (in addition to thefirst t

Strany 160

242 AMD Geode™ LX Processors Data Book Graphics Processor33234H6.3.2.1 Rotating BLTsThis feature of the GP allows bitmaps to be rotated 90°,180° or 27

Strany 161

AMD Geode™ LX Processors Data Book 243Graphics Processor 33234H6.3.2.4 Palletized Color SupportIf the Preserve LUT Data bit is set in theGP_CH3_MODE_

Strany 162 - DM_CONFIG1_MSR Register Map

244 AMD Geode™ LX Processors Data Book Graphics Processor33234H6.3.2.5 Anti-Aliased Text SupportChannel 3 can be setup to fetch 4-bpp alpha channel da

Strany 163 - DM_PFLOCK_MSR Register Map

AMD Geode™ LX Processors Data Book 245Graphics Processor 33234H6.3.2.8 Channel 3 Host SourceChannel 3 also supports host source data writes. When the

Strany 164

246 AMD Geode™ LX Processors Data Book Graphics Processor33234H6.3.4 Vector OperationGenerating a vector requires a similar setup to a BLT. Reg-isters

Strany 165 - RCONF_A0_BF_MSR Register Map

AMD Geode™ LX Processors Data Book 247Graphics Processor 33234H6.3.6.2 Color PatternsColor patterns are enabled by selecting the color patternmode in

Strany 166 - RCONF_E0_FF_MSR Register Map

248 AMD Geode™ LX Processors Data Book Graphics Processor33234HIn 16-bpp mode, there is a total of two lines of pattern, each line with eight pixels a

Strany 167 - RCONF_SMM_MSR Register Map

AMD Geode™ LX Processors Data Book 249Graphics Processor 33234H6.3.7 8x8 Color PatternsThe new channel 3 hardware provides the capability of per-form

Strany 168 - RCONF_DMM_MSR Register Map

AMD Geode™ LX Processors Data Book 25Signal Definitions 33234HFigure 3-2. BGU481 Ball Assignment Diagram123456789101112131415161718192021222324252627

Strany 169 - RCONFx_MSR Bit Descriptions

250 AMD Geode™ LX Processors Data Book Graphics Processor33234H6.3.8.2 Host SourceFor source data that is not already in the frame bufferregion of mem

Strany 170

AMD Geode™ LX Processors Data Book 251Graphics Processor 33234H6.3.8.3 Source ExpansionThe Graphics Processor contains hardware support forcolor expa

Strany 171

252 AMD Geode™ LX Processors Data Book Graphics Processor33234H6.3.11 Image Compositing Using AlphaWhereas the raster operation allows different strea

Strany 172 - DC_INDEX_MSR Register Map

AMD Geode™ LX Processors Data Book 253Graphics Processor 33234HA over B 1 1-αΑDisplay image A on top of image B. Wherever image A is transpar-ent, di

Strany 173 - DC_TAG_MSR Bit Descriptions

254 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4 Graphics Processor Register DefinitionsThe registers associate

Strany 174 - DC_TAG_I_MSR Register Map

AMD Geode™ LX Processors Data Book 255Graphics Processor Register Definitions 33234H10h R/W Color Config Source Color Foreground (GP_SRC_COLOR_FG)000

Strany 175 - L1DTLB_INDEX_MSR Register Map

256 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.1 Standard GeodeLink™ Device (GLD) MSRs6.4.1.1 GLD Capabilitie

Strany 176 - L1DTLB_LRU_MSR Register Map

AMD Geode™ LX Processors Data Book 257Graphics Processor Register Definitions 33234H6.4.1.3 GLD SMI MSR (GLD_MSR_SMI)This MSR contains the SMI and Ma

Strany 177 - L1DTLB_ENTRY_MSR Register Map

258 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.1.5 GLD Power Management MSR (GLD_MSR_PM)This MSR contains the

Strany 178 - L2TLB_INDEX_MSR Register Map

AMD Geode™ LX Processors Data Book 259Graphics Processor Register Definitions 33234H6.4.2 Graphics Processor Configuration Registers6.4.2.1 Destinati

Strany 179 - L2TLB_LRU_MSR Register Map

26 AMD Geode™ LX Processors Data Book Signal Definitions33234HBall No.Signal Name (Note 1)Type(PD)Buffer TypeA1 VSSGND ---A2 VMEMPWR ---A3 VSSGND ---A

Strany 180 - L2TLB_ENTRY_MSR Register Map

260 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.3 Vector Error (GP_VEC_ERR)This register specifies the axial

Strany 181

AMD Geode™ LX Processors Data Book 261Graphics Processor Register Definitions 33234H6.4.2.5 BLT Width/Height (GP_WID_HEIGHT)This register is used to

Strany 182 - DM_BIST_MSR Bit Descriptions

262 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.7 Source Color Foreground (GP_SRC_COLOR_FG)When source data

Strany 183 - BC_CONFIG0_MSR Register Map

AMD Geode™ LX Processors Data Book 263Graphics Processor Register Definitions 33234H6.4.2.8 Source Color Background (GP_SRC_COLOR_BG)When source data

Strany 184

264 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.9 Pattern Color (GP_PAT_COLOR_x) In solid pattern mode, the

Strany 185 - MSR_LOCK_MSR Register Map

AMD Geode™ LX Processors Data Book 265Graphics Processor Register Definitions 33234H6.4.2.10 Pattern Data (GP_PAT_DATA_x)In solid pattern mode, these

Strany 186 - RTSC_TSC_MSR Bit Descriptions

266 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234HGP_RASTER_MODE Bit DescriptionsBit Name Description31:28 BPP/FMT C

Strany 187 - L2_CONFIG_MSR Register Map

AMD Geode™ LX Processors Data Book 267Graphics Processor Register Definitions 33234H6.4.2.12 Vector Mode (GP_VECTOR_MODE) Writing to this register co

Strany 188 - L2_INDEX_MSR Bit Descriptions

268 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.13 BLT Mode (GP_BLT_MODE)Writing to this register configures

Strany 189 - L2_TAG_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 269Graphics Processor Register Definitions 33234H6.4.2.14 Status and Reset (GP_BLT_STATUS, GP_RESET)This register

Strany 190 - L2_BIST_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 27Signal Definitions 33234HH2 VSSGND ---H3 DQS1 I/O DDRH4 SDCLK1N O DDRCLKH28 SDCLK3N O DDRCLKH29 DQM6 I/O DDRH30

Strany 191

270 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.16 Base Offset (GP_BASE_OFFSET)This register is used to defi

Strany 192

AMD Geode™ LX Processors Data Book 271Graphics Processor Register Definitions 33234H6.4.2.18 Command Bottom (GP_CMD_BOT)This register defines the end

Strany 193 - PMODE_MSR Bit Descriptions

272 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.20 Command Write (GP_CMD_WRITE)This register points to the n

Strany 194 - BXDR3_BXDR2_MSR Register Map

AMD Geode™ LX Processors Data Book 273Graphics Processor Register Definitions 33234H6.4.2.22 Stride (GP_CH3_MODE_STR)The GP_ CH3_MODE_STR register ha

Strany 195 - BXDR6_BXDR7_MSR Register Map

274 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H29 X X Direction for Fetch. Data is reversed if fetch direction do

Strany 196

AMD Geode™ LX Processors Data Book 275Graphics Processor Register Definitions 33234H6.4.2.23 Width/Height (GP_CH3_WIDHI)This register is used to spec

Strany 197 - BDRx_MSR Bit Descriptions

276 AMD Geode™ LX Processors Data Book Graphics Processor Register Definitions33234H6.4.2.25 LUT Index (GP_LUT_INDEX)This register is used to initiali

Strany 198 - BDR7_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 277Graphics Processor Register Definitions 33234H6.4.2.27 Interrupt Control (GP_INT_CNTRL)This register is used to

Strany 199

278 AMD Geode™ LX Processors Data Book Display Controller33234H6.5 Display ControllerThe Display Controller (DC) module retrieves graphics,video, and

Strany 200

AMD Geode™ LX Processors Data Book 279Display Controller 33234HThe GUI block, shown in Figure 6-13, provides sophisti-cated graphics functionality su

Strany 201

28 AMD Geode™ LX Processors Data Book Signal Definitions33234HY2 DAVSSAGND ---Y3 VIOPWR ---Y4 VSSGND ---Y28 VCOREPWR ---Y29 VSSGND ---Y30 RESET# I PCI

Strany 202 - FP_MODE_MSR Bit Descriptions

280 AMD Geode™ LX Processors Data Book Display Controller33234HThe VGA block, shown in Figure 6-14, provides hardwaresupport for a compatible VGA solu

Strany 203 - FPU_TW_MSR Register Map

AMD Geode™ LX Processors Data Book 281Display Controller 33234H6.5.1 GUI Functional Overview6.5.1.1 Display Mode SupportThe display modes listed in T

Strany 204 - FPU_MAP_MSR Bit Descriptions

282 AMD Geode™ LX Processors Data Book Display Controller33234H1280 x 1024 8, 16, or 24/32 60 108.000 2008, 16, or 24/32 70 129.600 2008, 16, or 24/32

Strany 205 - FPU_MRx_MSR Bit Descriptions

AMD Geode™ LX Processors Data Book 283Display Controller 33234H6.5.1.2 Display FIFOThe DC module incorporates a 512-entry x 64-bit displayFIFO that q

Strany 206 - FPU_ERx_MSR Bit Descriptions

284 AMD Geode™ LX Processors Data Book Display Controller33234HCursor/Icon Buffer FormatsIn 2-bpp mode, the cursor buffer is stored as a linear dis-pl

Strany 207

AMD Geode™ LX Processors Data Book 285Display Controller 33234H6.5.1.4 Display Refresh CompressionTo reduce the system memory contention caused by th

Strany 208 - CPUIDx_MSR Bit Descriptions

286 AMD Geode™ LX Processors Data Book Display Controller33234H6.5.1.9 Video Overlay SupportThe GUI block also supports a video overlay function. TheD

Strany 209 - 6.0Integrated Functions

AMD Geode™ LX Processors Data Book 287Display Controller 33234H6.5.1.10 Output FormatsVideo Output Data SequencingThe order that video data is transm

Strany 210 - GeodeLink™ Memory Controller

288 AMD Geode™ LX Processors Data Book Display Controller33234H6.5.4 VGA Block Functional OverviewThe VGA block provides full hardware support for a V

Strany 211

AMD Geode™ LX Processors Data Book 289Display Controller 33234H6.5.5.2 Graphics ControllerThe graphics controller manages the CPU interaction withvid

Strany 212

AMD Geode™ LX Processors Data Book 29Signal Definitions 33234HAK4 DRGB14 O (PD) 24/Q5VOP9 OAK5 VSSGND ---AK6 DRGB1 O (PD) 24/Q5VOP6 OAK7 DRGB4 O (PD)

Strany 213

290 AMD Geode™ LX Processors Data Book Display Controller33234H6.5.5.3 Write ModesThere are four write modes supported by the graphics con-troller (mo

Strany 214

AMD Geode™ LX Processors Data Book 291Display Controller 33234H6.5.5.4 Read ModesThere are two read modes provided to assist the CPU withgraphics ope

Strany 215 - Figure 6-7. Request Pipeline

292 AMD Geode™ LX Processors Data Book Display Controller33234HFigure 6-19. Color Compare Operation8x4 Input ANDCompare Result [7:0]CC3 CC2 CC1 CC0Mem

Strany 216 - Figure 6-8. DDR Reads

AMD Geode™ LX Processors Data Book 293Display Controller 33234H6.5.6 Graphics Scaler/FilterThe DC incorporates a 3x5 tap filter to be used for up/dow

Strany 217 - Figure 6-9. DDR Writes

294 AMD Geode™ LX Processors Data Book Display Controller33234HFigure 6-20. Graphics Filter Block Diagram (Continued)2 PixelLatchxxx+xxx+2 PixelLatchH

Strany 218 - 6.1.2 Power Control

AMD Geode™ LX Processors Data Book 295Display Controller 33234HTo support the flicker filter, the scaling filter then feeds twoadditional line buffer

Strany 219

296 AMD Geode™ LX Processors Data Book Display Controller33234H6.5.7 Color Key EliminationAdditional logic, not shown in the diagrams, is used to pre-

Strany 220 - GLD_MSR_CAP Register

AMD Geode™ LX Processors Data Book 297Display Controller 33234H6.5.9 Interlaced ModesFor interlaced modes, the V_ACTIVE and V_TOTAL fieldsare configu

Strany 221 - GLD_MSR_ERROR Register Map

298 AMD Geode™ LX Processors Data Book Display Controller33234H6.5.10 Interlaced Timing ExamplesFigure 6-22 shows how the DC's timing registers a

Strany 222 - GLD_MSR_PM Bit Descriptions

AMD Geode™ LX Processors Data Book 299Display Controller 33234HTable 6-44. Timing Register Settings for Interlaced ModesTiming Set Parameter Odd Regi

Strany 223 - MC_CF_BANK23 Bit Descriptions

AMD Geode™ LX Processors Data Book 3Contents 33234HContentsList of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Strany 224 - MC_CF_BANK67 Bit Descriptions

30 AMD Geode™ LX Processors Data Book Signal Definitions33234HSignal Name Ball No.AD0 AJ19AD1 AH19AD2 AL20AD3 AK20AD4 AK19AD5 AH21AD6 AJ21AD7 AL19AD8

Strany 225 - MC_CF_BANKAB Bit Descriptions

300 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6 Display Controller Register DescriptionsThis section provides

Strany 226 - MC_CF_BANKEF Bit Descriptions

AMD Geode™ LX Processors Data Book 301Display Controller Register Descriptions 33234H020h R/W DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFF

Strany 227 - MC_CF07_DATA Bit Descriptions

302 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H08Ch R/W DC Dirty/Valid RAM Access (DC_DV_ACCESS) 0000000xh Page

Strany 228

AMD Geode™ LX Processors Data Book 303Display Controller Register Descriptions 33234HTable 6-48. VGA Block Configuration Register SummaryDC Memory Of

Strany 229 - MC_CF8F_DATA Register Map

304 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234HTable 6-50. VGA Block Extended Register SummaryVGA CRTC Index Typ

Strany 230 - MC_CF8F_DATA Bit Descriptions

AMD Geode™ LX Processors Data Book 305Display Controller Register Descriptions 33234H6.6.1 Standard GeodeLink™ Device (GLD) Registers (MSRs)6.6.1.1 G

Strany 231 - MC_CF1017_DATA Register Map

306 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.1.3 GLIU0 Device SMI MSR (GLD_MSR_SMI)MSR Address 80002002hTy

Strany 232 - MC_CFPERF_CNT1 Register Map

AMD Geode™ LX Processors Data Book 307Display Controller Register Descriptions 33234H40 SEQIOR_SMI Sequencer Register Read SMI. Reading a 1 indicates

Strany 233 - MC_CFCLK_DBUG Register Map

308 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.1.4 GLD Error MSR (GLD_MSR_ERROR)9GFXIOW_MSKGraphics Controll

Strany 234

AMD Geode™ LX Processors Data Book 309Display Controller Register Descriptions 33234HGLD_MSR_ERROR Bit DescriptionsBit Name Description63:38 RSVD Res

Strany 235 - MC_CFPG_OPEN Bit Descriptions

AMD Geode™ LX Processors Data Book 31Signal Definitions 33234HDRGB7 AJ8DRGB8 AJ2DRGB9 AK3DRGB10 AL3DRGB11 AH5DRGB12 AJ4DRGB13 AL4DRGB14 AK4DRGB15 AJ5

Strany 236 - MC_CF_PMCTR Bit Descriptions

310 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.1.5 GLD Power Management MSR (GLD_MSR_PM)6.6.1.6 GLIU0 Device

Strany 237 - 6.3 Graphics Processor

AMD Geode™ LX Processors Data Book 311Display Controller Register Descriptions 33234H6.6.2 Display Controller Specific MSRs6.6.2.1 SPARE MSR6.6.2.2 D

Strany 238 - Graphics Processor

312 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.3 Configuration and Status RegistersAll DC registers are DWOR

Strany 239 - 6.3.1 Command Buffer

AMD Geode™ LX Processors Data Book 313Display Controller Register Descriptions 33234HDC_UNLOCK Bit DescriptionsBit Name Description31:16 RSVD Reserve

Strany 240

314 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.3.2 DC General Configuration (DC_GENERAL_CFG)This register co

Strany 241 - Table 6-12. Bit Descriptions

AMD Geode™ LX Processors Data Book 315Display Controller Register Descriptions 33234H24 SIGE Signature Enable. Effective immediately.0: CRC Signature

Strany 242

316 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H11:8 DFHPSL Display-FIFO High Priority Start Level. This field sp

Strany 243

AMD Geode™ LX Processors Data Book 317Display Controller Register Descriptions 33234H6.6.3.3 DC Display Configuration (DC_DISPLAY_CFG)This register c

Strany 244

318 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H9:8 DISP_MODE Display Mode. Bits per pixel.00: 8-bpp (also used i

Strany 245 - 6.3.3 BLT Operation

AMD Geode™ LX Processors Data Book 319Display Controller Register Descriptions 33234H6.6.3.4 DC Arbitration Configuration (DC_ARB_CFG)This register c

Strany 246 - 6.3.6 Pattern Generation

32 AMD Geode™ LX Processors Data Book Signal Definitions33234HVOP13 AL3VOP14 AK3VOP15 AJ2VOP_BLANK AE4VOPCLK AE1VOP_HSYNC AE3VOP_VSYNC AD3VMEM (Total

Strany 247

320 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H3 HPEN_2LB_INV High Priority Enable when Any Two Line Buffers Inv

Strany 248

AMD Geode™ LX Processors Data Book 321Display Controller Register Descriptions 33234H6.6.4 Memory Organization RegistersThe graphics memory region is

Strany 249

322 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.4.2 DC Compression Buffer Start Address (DC_CB_ST_OFFSET)This

Strany 250

AMD Geode™ LX Processors Data Book 323Display Controller Register Descriptions 33234H6.6.4.4 DC Video Y Buffer Start Address Offset (DC_VID_Y_ST_OFFS

Strany 251 - 6.3.9 Destination Data

324 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.4.6 DC Video V Buffer Start Address Offset (DC_VID_V_ST_OFFSE

Strany 252

AMD Geode™ LX Processors Data Book 325Display Controller Register Descriptions 33234H6.6.4.8 DC Line Size (DC_LINE_SIZE)This register specifies the n

Strany 253

326 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.4.9 DC Graphics Pitch (DC_GFX_PITCH)This register stores the

Strany 254 - (GP_SRC_OFFSET)

AMD Geode™ LX Processors Data Book 327Display Controller Register Descriptions 33234H6.6.5 Timing RegistersThe DC timing registers control the genera

Strany 255 - 00000000h Page 272

328 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.5.1 DC Horizontal and Total Timing (DC_H_ACTIVE_TIMING)This r

Strany 256

AMD Geode™ LX Processors Data Book 329Display Controller Register Descriptions 33234H6.6.5.2 DC CRT Horizontal Blanking Timing (DC_H_BLANK_TIMING)Thi

Strany 257 - GLD_MSR_SMI Bit Descriptions

AMD Geode™ LX Processors Data Book 33Signal Definitions 33234H3.4 Signal Descriptions3.4.1 System Interface SignalsSignal NameBall No. Type f V Descr

Strany 258

330 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.5.4 DC Vertical and Total Timing (DC_V_ACTIVE_TIMING)This reg

Strany 259 - GP_SRC_OFFSET Register Map

AMD Geode™ LX Processors Data Book 331Display Controller Register Descriptions 33234H6.6.5.5 DC CRT Vertical Blank Timing (DC_V_BLANK_TIMING)This reg

Strany 260 - GP_STRIDE Register Map

332 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.5.7 DC Frame Buffer Active Region Register (DC_FB_ACTIVE)6.6.

Strany 261 - GP_VEC_LEN Bit Descriptions

AMD Geode™ LX Processors Data Book 333Display Controller Register Descriptions 33234H6.6.6.2 DC Cursor Y Position (DC_CURSOR_Y)This register contains

Strany 262 - GP_SRC_COLOR_FG Register Map

334 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234HDC_LINE_CNT/STATUS Register Map3130292827262524232221201918171615

Strany 263 - GP_SRC_COLOR_BG Register Map

AMD Geode™ LX Processors Data Book 335Display Controller Register Descriptions 33234H6.6.7 Palette Access FIFO Diagnostic RegistersThe Palette Access

Strany 264 - GP_PAT_COLOR_x Register Map

336 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.7.2 DC Palette Data (DC_PAL_DATA)This register contains the d

Strany 265 - GP_RASTER_MODE Register Map

AMD Geode™ LX Processors Data Book 337Display Controller Register Descriptions 33234H6.6.7.4 DC Compression FIFO Diagnostic (DC_CFIFO_DIAG)This regis

Strany 266 - 01: Mono pattern

338 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.8 Video Downscaling6.6.8.1 DC Video Downscaling Delta (DC_VID

Strany 267 - GP_VECTOR_MODE Register Map

AMD Geode™ LX Processors Data Book 339Display Controller Register Descriptions 33234H6.6.9 GLIU Control Registers6.6.9.1 DC GLIU0 Memory Offset (DC_G

Strany 268 - GP_BLT_MODE Bit Descriptions

34 AMD Geode™ LX Processors Data Book Signal Definitions33234HTDP AL17 A Analog N/A Thermal Diode Positive (TDP). TDP is the positive terminal of the

Strany 269 - GP_HST_SRC Register Map

340 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.9.3 DC Dirty/Valid RAM Access (DC_DV_ACCESS)11:10 DV_LINE_SIZ

Strany 270 - GP_CMD_TOP Bit Descriptions

AMD Geode™ LX Processors Data Book 341Display Controller Register Descriptions 33234H6.6.10 Graphics Scaling Control Registers6.6.10.1 DC Graphics Fi

Strany 271 - GP_CMD_READ Bit Descriptions

342 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.10.2 DC IRQ/Filter Control (DC_IRQ_FILT_CTL)DC Memory Offset

Strany 272 - GP_CH3_OFFSET Register Map

AMD Geode™ LX Processors Data Book 343Display Controller Register Descriptions 33234H6.6.10.3 DC Filter Coefficient Data Register 1 (DC_FILT_COEFF1)A

Strany 273 - GP_CH3_MODE_STR Register Map

344 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.10.4 DC Filter Coefficient Data Register 2 (DC_FILT_COEFF2)An

Strany 274

AMD Geode™ LX Processors Data Book 345Display Controller Register Descriptions 33234H6.6.11.2 DC VBI Odd Control (DC_VBI_ODD_CTL)Settings written to

Strany 275 - GP_CH3_HSRC Bit Descriptions

346 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.11.4 DC VBI Odd Line Enable (DC_VBI_LN_ODD)Settings written t

Strany 276

AMD Geode™ LX Processors Data Book 347Display Controller Register Descriptions 33234H6.6.11.6 DC VBI Pitch and Size (DC_VBI_PITCH)6.6.12 Color Key Co

Strany 277 - GP_INT_CNTRL Bit Descriptions

348 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.12.2 DC Color Key Mask (DC_CLR_KEY_MASK)6.6.12.3 DC Color Key

Strany 278 - 6.5 Display Controller

AMD Geode™ LX Processors Data Book 349Display Controller Register Descriptions 33234H6.6.12.5 DC Interrupt (DC_IRQ)DC_CLR_KEY_Y Bit DescriptionsBit N

Strany 279

AMD Geode™ LX Processors Data Book 35Signal Definitions 33234H3.4.3 Memory Interface Signals (DDR)Signal Name Ball No. Type f V DescriptionSDCLK[5:0]

Strany 280 - Display Controller

350 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.13 Interrupt and GenLock Registers6.6.13.1 DC GenLock Contro

Strany 281 - Table 6-32. Display Modes

AMD Geode™ LX Processors Data Book 351Display Controller Register Descriptions 33234H6.6.14 Even Field Video Address Registers6.6.14.1 DC Even Field

Strany 282

352 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.14.2 DC Even Field Video U Start Address Offset (DC_VID_EVEN_

Strany 283

AMD Geode™ LX Processors Data Book 353Display Controller Register Descriptions 33234H6.6.15 Even Field Vertical Timing Registers6.6.15.1 DC Vertical

Strany 284

354 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.15.2 DC CRT Vertical Blank Timing for Even Fields (DC_V_BLANK

Strany 285

AMD Geode™ LX Processors Data Book 355Display Controller Register Descriptions 33234H6.6.16 VGA Block Configuration Registers6.6.16.1 VGA Configurati

Strany 286 - Table 6-36. Video Bandwidth

356 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.17 VGA Block Standard Registers6.6.17.1 VGA Miscellaneous Out

Strany 287

AMD Geode™ LX Processors Data Book 357Display Controller Register Descriptions 33234H6.6.17.2 VGA Input Status Register 06.6.17.3 VGA Input Status Re

Strany 288 - Table 6-39. VGA Text Modes

358 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.18 VGA Sequencer RegistersThe Sequencer registers are accesse

Strany 289

AMD Geode™ LX Processors Data Book 359Display Controller Register Descriptions 33234H6.6.18.4 VGA Clocking Mode6.6.18.5 VGA Map MaskThese bits enable

Strany 290

36 AMD Geode™ LX Processors Data Book Signal Definitions33234HDQM[7:0] N30, H29, C24, A19, B10, A6, G2, M1I/O 166-400 Mb/s 2.5 Data Mask Control Bits.

Strany 291

360 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.18.6 VGA Character Map SelectCharacter Map A (bits [5,3:2]) a

Strany 292

AMD Geode™ LX Processors Data Book 361Display Controller Register Descriptions 33234H6.6.19 VGA CRT Controller RegistersThe CRTC registers are access

Strany 293 - 6.5.6 Graphics Scaler/Filter

362 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.1 CRTC Index Table 6-54. CRTC Registers SummaryIndex Type

Strany 294

AMD Geode™ LX Processors Data Book 363Display Controller Register Descriptions 33234H6.6.19.2 CRTC Data 6.6.19.3 Horizontal Total6.6.19.4 Horizontal

Strany 295

364 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.6 Horizontal Blank End 6.6.19.7 Horizontal Sync Start 6.6.

Strany 296

AMD Geode™ LX Processors Data Book 365Display Controller Register Descriptions 33234H6.6.19.9 Vertical Total 6.6.19.10 OverflowThese are the high-ord

Strany 297

366 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.12 Maximum Scan Line 6.6.19.13 Cursor Start6:5 BYPE_PAN By

Strany 298

AMD Geode™ LX Processors Data Book 367Display Controller Register Descriptions 33234H6.6.19.14 Cursor End6.6.19.15 Start Address High6.6.19.16 Start

Strany 299

368 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.18 Cursor Location Low6.6.19.19 Vertical Sync Start6.6.19.

Strany 300

AMD Geode™ LX Processors Data Book 369Display Controller Register Descriptions 33234H6.6.19.21 Vertical Display Enable End 6.6.19.22 Offset6.6.19.23

Strany 301 - (DC_GLIU0_MEM_OFFSET)

AMD Geode™ LX Processors Data Book 37Signal Definitions 33234H3.4.5 PCI Interface SignalsSignal Name Ball No. Type f V DescriptionAD[31:0] See Table

Strany 302 - (DC_VID_EVEN_V_ST_OFFSET)

370 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.24 Vertical Blank Start 6.6.19.25 Vertical Blank End 6.6.1

Strany 303

AMD Geode™ LX Processors Data Book 371Display Controller Register Descriptions 33234HTable 6-55 illustrates the various frame buffer addressing schem

Strany 304

372 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.19.27 Line Compare6.6.19.28 CPU Data Latch State6.6.19.29 Att

Strany 305

AMD Geode™ LX Processors Data Book 373Display Controller Register Descriptions 33234H6.6.19.30 Attribute Index State 6.6.20 VGA Graphics Controller R

Strany 306

374 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.20.2 VGA Graphics Controller Data6.6.20.3 VGA Set/Reset Bits

Strany 307

AMD Geode™ LX Processors Data Book 375Display Controller Register Descriptions 33234H6.6.20.5 VGA Color Compare Bits [3:0] specify a compare value th

Strany 308

376 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.20.7 VGA Read Map Select 6.6.20.8 VGA Graphics Mode Index 04h

Strany 309

AMD Geode™ LX Processors Data Book 377Display Controller Register Descriptions 33234H6.6.20.9 VGA Miscellaneous 1:0 WR_MD Write Mode. This field spec

Strany 310

378 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.20.10 VGA Color Don’t Care6.6.20.11 VGA Bit Mask6.6.21 Attrib

Strany 311 - DC_RAM_CTL_MSR Register Map

AMD Geode™ LX Processors Data Book 379Display Controller Register Descriptions 33234H6.6.21.1 Attribute Controller Index/DataThe attribute controller

Strany 312 - DC_UNLOCK Register Map

38 AMD Geode™ LX Processors Data Book Signal Definitions33234HRESET# Y30 I 0-1 Mb/s 3.3 PCI Reset. RESET# aborts all operations in progress and places

Strany 313 - DC_UNLOCK Bit Descriptions

380 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.21.3 Attribute Mode Control6.6.21.4 Overscan Color Index 10hT

Strany 314 - DC_GENERAL_CFG Register Map

AMD Geode™ LX Processors Data Book 381Display Controller Register Descriptions 33234H6.6.21.5 Color Plane Enable 6.6.21.6 Horizontal Pel Panning Inde

Strany 315 - , or 4 KB

382 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.21.7 Color Select6.6.22 Video DAC RegistersVideo DAC palette

Strany 316 - 3VIDE Video Enable

AMD Geode™ LX Processors Data Book 383Display Controller Register Descriptions 33234H6.6.22.1 Video DAC Palette Address6.6.22.2 Video DAC State6.6.22

Strany 317 - DC_DISPLAY_CFG Register Map

384 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.22.4 Video DAC Palette Mask6.6.23 VGA Block Extended Register

Strany 318

AMD Geode™ LX Processors Data Book 385Display Controller Register Descriptions 33234H6.6.23.1 ExtendedRegisterLock6.6.23.2 ExtendedModeControl 6.6.23

Strany 319 - DC_ARB_CFG Bit Descriptions

386 AMD Geode™ LX Processors Data Book Display Controller Register Descriptions33234H6.6.23.4 WriteMemoryAperture 6.6.23.5 ReadMemoryAperture 6.6.23.6

Strany 320

AMD Geode™ LX Processors Data Book 387Display Controller Register Descriptions 33234H6.6.23.7 BlinkCounter This register is for simulation and test o

Strany 321 - DC_FB_ST_OFFSET

388 AMD Geode™ LX Processors Data Book Video Processor33234H6.7 Video ProcessorThe Video Processor (VP) module provides a high-perfor-mance, low-power

Strany 322 - DC_CB_ST_OFFSET Register Map

AMD Geode™ LX Processors Data Book 389Video Processor 33234HFigure 6-23. Video Processor Block DiagramVideo DataInterface(YUV)ControlRegistersInterfa

Strany 323

AMD Geode™ LX Processors Data Book 39Signal Definitions 33234HDEVSEL# AK25 I/O 33-66 Mb/s 3.3 Device Select. DEVSEL# indicates that the driv-ing devi

Strany 324 - DC_DV_TOP Register Map

390 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.2 Functional DescriptionThe VP receives the input video stream in either YUV(4:2:2 or

Strany 325 - DC_LINE_SIZE Bit Descriptions

AMD Geode™ LX Processors Data Book 391Video Processor 33234H6.7.2.1 Video FormatterThe Video Processor module accepts video data at a rateasynchronou

Strany 326 - DC_VID_YUV_PITCH Register Map

392 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.2.3 Horizontal DownscalingThe Video Processor module supports horizontal down-scaling

Strany 327 - 6.6.5 Timing Registers

AMD Geode™ LX Processors Data Book 393Video Processor 33234H6.7.3 X and Y UpscalerAfter the video data has been buffered, the upscaling algo-rithm is

Strany 328 - RSVD H_TOTAL RSVD H_ACTIVE

394 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.5 Video OverlayVideo data is mixed with graphics data according to thevideo window pos

Strany 329 - DC_H_SYNC_TIMING Register Map

AMD Geode™ LX Processors Data Book 395Video Processor 33234HFigure 6-27. Mixer Block DiagramCSC_VIDEOVideo YUVGraphicsGV_PAL_BPRGB/YUVVSYNCCurrent Pi

Strany 330 - RSVD V_TOTAL RSVD V_ACTIVE

396 AMD Geode™ LX Processors Data Book Video Processor33234HFigure 6-28. Color Key and Alpha-Blending LogicNoYe sYe sNoYe sNoNoYe sNoYe sNotes:1) VG_C

Strany 331 - DC_V_SYNC_TIMING Register Map

AMD Geode™ LX Processors Data Book 397Video Processor 33234HTable 6-60 represents the same logic that is displayed in Figure 6-28 on page 396.6.7.5.2

Strany 332 - DC_CURSOR_X Bit Descriptions

398 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.6 Video Output Port6.7.6.1 Functional OverviewThe Video Output Port (VOP) receives YUV

Strany 333 - DC_CURSOR_Y Bit Descriptions

AMD Geode™ LX Processors Data Book 399Video Processor 33234H6.7.6.3 HBLANK and VBLANK SignalsHBLANK and VBLANK signals are different from HSYNCand VS

Strany 334 - 20h[27:0]) has not

4 AMD Geode™ LX Processors Data Book Contents33234H6.0 Integrated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Strany 335 - DC_PAL_ADDRESS Register Map

40 AMD Geode™ LX Processors Data Book Signal Definitions33234H3.4.6 TFT Display Interface SignalsSignal Name Ball No. Type f V DescriptionDRGB[31:24]D

Strany 336 - DC_DFIFO_DIAG Register Map

400 AMD Geode™ LX Processors Data Book Video Processor33234HFigure 6-32. HBLANK and VBLANK for Lines 263, 525Figure 6-33. HBLANK and VBLANK for Lines

Strany 337 - DC_CFIFO_DIAG Register Map

AMD Geode™ LX Processors Data Book 401Video Processor 33234H6.7.6.4 Interface to Video ProcessorThe output from the Video Processor is connected via

Strany 338 - DC_VID_DS_DELTA Register Map

402 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.6.5 Operating ModesBT.656 ModeBT.656 is the basic standard that specifies the encoding

Strany 339 - DV_CTL Bit Descriptions

AMD Geode™ LX Processors Data Book 403Video Processor 33234HVIP 2.0 Modes (8 or 16 bits)VIP 2.0 mode builds on VIP 1.1 with the following changes/add

Strany 340 - DC_DV_ACCESS Bit Descriptions

404 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.6.6 New VIP 2.0 Video FlagsFour bits are defined (shown in Table 6-64) by the VIPspeci

Strany 341 - DC_GFX_SCALE Bit Descriptions

AMD Geode™ LX Processors Data Book 405Video Processor 33234H6.7.7 Flat Panel Display Controller6.7.7.1 FP Functional OverviewThe flat panel (FP) disp

Strany 342 - DC_IRQ_FILT_CTL Register Map

406 AMD Geode™ LX Processors Data Book Video Processor33234H6.7.7.3 FP Functional DescriptionThe FP connects to the RGB port of the video mixer.LCD In

Strany 343 - DC_FILT_COEFF1 Register Map

AMD Geode™ LX Processors Data Book 407Video Processor 33234HMaximum FrequencyThe FP will operate at a DOTCLK frequency of up to 170MHz. There is no m

Strany 344 - DC_VBI_EVEN_CTL Register Map

408 AMD Geode™ LX Processors Data Book Video Processor33234HFigure 6-37. Dithered 8x8 Pixel PatternAll discussions to this point have referred to a 6-

Strany 345 - DC_VBI_HOR Bit Descriptions

AMD Geode™ LX Processors Data Book 409Video Processor 33234HFigure 6-38. N-Bit Dithering Pattern Schemes15 131412000001010011100111101110000 001 010

Strany 346 - DC_VBI_LN_EVEN Register Map

AMD Geode™ LX Processors Data Book 41Signal Definitions 33234H 3.4.7 CRT Display Interface SignalsSignal Name Ball No. Type f V DescriptionHSYNC AE3

Strany 347 - DC_CLR_KEY Bit Descriptions

410 AMD Geode™ LX Processors Data Book Video Processor33234HCRC SignatureThe FP contains hardware/logic that performs CyclicalRedundancy Checks (CRCs)

Strany 348 - DC_CLR_KEY_Y Register Map

AMD Geode™ LX Processors Data Book 411Video Processor 33234H6.7.8 VP Resolution TableSupported CRT and flat panel resolutions of the VP areprovided i

Strany 349 - DC_IRQ Bit Descriptions

412 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8 Video Processor Register DescriptionsThis section provides infor

Strany 350 - DC_GENLK_CTL Bit Descriptions

AMD Geode™ LX Processors Data Book 413Video Processor Register Descriptions 33234H050h R/W Miscellaneous (MISC) 00000000_00000C00h Page 430058h R/W C

Strany 351 - RSVD OFFSET

414 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234HFlat Panel400h R/W Panel Timing Register 1 (PT1) 00000000_00000000h

Strany 352

AMD Geode™ LX Processors Data Book 415Video Processor Register Descriptions 33234H6.8.1 Standard GeodeLink™ Device MSRs6.8.1.1 GLD Capabilities MSR (

Strany 353

416 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H15 FPC Simultaneous Flat Panel (or VOP) and CRT. Primary display is

Strany 354

AMD Geode™ LX Processors Data Book 417Video Processor Register Descriptions 33234H6.8.1.3 GLD SMI MSR (GLD_MSR_SMI)The Video Processor does not produ

Strany 355 - VGA_STATUS Bit Descriptions

418 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.1.5 GLD Power Management MSR (GLD_MSR_PM)6.8.1.6 GLD Diagnostic

Strany 356

AMD Geode™ LX Processors Data Book 419Video Processor Register Descriptions 33234H6.8.2 Video Processor Module Specific MSRs6.8.2.1 VP Diagnostic MSR

Strany 357

42 AMD Geode™ LX Processors Data Book Signal Definitions33234HFor additional electrical details on pins, refer to Section 7.0 "Electrical Specifi

Strany 358

420 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.2.2 Pad Select MSR (MSR_PADSEL)MSR Address 48002011hTyp e R /WRe

Strany 359

AMD Geode™ LX Processors Data Book 421Video Processor Register Descriptions 33234H6.8.3 Video Processor Module Control/Configuration Registers6.8.3.1

Strany 360 - Table 6-52. Font Table

422 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.2 Display Configuration (DCFG)5 SC_BYP Scaler Bypass. Bypass s

Strany 361

AMD Geode™ LX Processors Data Book 423Video Processor Register Descriptions 33234HDCFG Bit DescriptionsBit Name Description63:32 RSVD (RO) Reserved (

Strany 362 - 00h Page 369

424 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.3 Video X Position (VX)2 VSYNC_EN CRT Vertical Sync Enable. En

Strany 363

AMD Geode™ LX Processors Data Book 425Video Processor Register Descriptions 33234H6.8.3.4 Video Y Position (VY)6.8.3.5 Video Scale (SCL)VP Memory Off

Strany 364

426 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.6 Video Color Key Register (VCK)30 GB (RO) GLIU Behind (Read O

Strany 365

AMD Geode™ LX Processors Data Book 427Video Processor Register Descriptions 33234H6.8.3.7 Video Color Mask (VCM)23:0 VID_CLR_KEY Video Color Key. The

Strany 366

428 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.8 Palette Address (PAR) 6.8.3.9 Palette Data (PDR)VP Memory Of

Strany 367

AMD Geode™ LX Processors Data Book 429Video Processor Register Descriptions 33234H6.8.3.10 Saturation Scale (SLR)VP Memory Offset 048hTyp e R /WReset

Strany 368

AMD Geode™ LX Processors Data Book 43Signal Definitions 33234HTable 3-7. Signal Behavior During and After ResetSignal Name Type BehaviorAD[31:0] PCI

Strany 369 - 6.6.19.23 Underline Location

430 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.11 Miscellaneous (MISC)VP Memory Offset 050hTyp e R /WReset Va

Strany 370

AMD Geode™ LX Processors Data Book 431Video Processor Register Descriptions 33234H6.8.3.12 CRT Clock Select (CCS)This register is made up of read onl

Strany 371

432 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.15 Video Downscaler Control (VDC)VXS Bit DescriptionsBit Name

Strany 372

AMD Geode™ LX Processors Data Book 433Video Processor Register Descriptions 33234H6.8.3.16 CRC Signature (CRC)VP Memory Offset 088hTyp e R /WReset Va

Strany 373

434 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.17 32-Bit CRC Signature (CRC32)6.8.3.18 Video De-Interlacing a

Strany 374

AMD Geode™ LX Processors Data Book 435Video Processor Register Descriptions 33234H17:16 A1P Alpha Window 1 Priority. Indicates the priority of alpha

Strany 375

436 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.19 Cursor Color Key (CCK) 8GFX_INS_VIDEOGraphics Window inside

Strany 376

AMD Geode™ LX Processors Data Book 437Video Processor Register Descriptions 33234H6.8.3.20 Cursor Color Mask (CCM)6.8.3.21 Cursor Color 1 (CC1)VP Mem

Strany 377

438 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.22 Cursor Color 2 (CC2)6.8.3.23 Alpha Window 1 X Position (A1X

Strany 378

AMD Geode™ LX Processors Data Book 439Video Processor Register Descriptions 33234H6.8.3.24 Alpha Window 1 Y Position (A1Y)6.8.3.25 Alpha Window 1 Col

Strany 379

44 AMD Geode™ LX Processors Data Book Signal Definitions33234H

Strany 380

440 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.26 Alpha Window 1 Control (A1T)A1C Bit Descriptions Bit Name D

Strany 381

AMD Geode™ LX Processors Data Book 441Video Processor Register Descriptions 33234H6.8.3.27 Alpha Window 2 X Position (A2X)A1T Bit Descriptions Bit Na

Strany 382 - 6.6.22 Video DAC Registers

442 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.28 Alpha Window 2 Y Position (A2Y) 6.8.3.29 Alpha Window 2 Col

Strany 383

AMD Geode™ LX Processors Data Book 443Video Processor Register Descriptions 33234H6.8.3.30 Alpha Window 2 Control (A2T)A2C Bit Descriptions Bit Name

Strany 384

444 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.31 Alpha Window 3 X Position (A3X)16 ALPHA2_WIN_ENAlpha Window

Strany 385

AMD Geode™ LX Processors Data Book 445Video Processor Register Descriptions 33234H6.8.3.32 Alpha Window 3 Y Position (A3Y) 6.8.3.33 Alpha Window 3 Co

Strany 386

446 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.34 Alpha Window 3 Control (A3T)A3C Bit Descriptions Bit Name D

Strany 387

AMD Geode™ LX Processors Data Book 447Video Processor Register Descriptions 33234H6.8.3.35 Video Request (VRR) 16 ALPHA3_WIN_ENAlpha Window 3 Enable.

Strany 388 - 6.7 Video Processor

448 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.36 Alpha Watch (AWT)Alpha values may be automatically incremen

Strany 389 - Video Processor Module

AMD Geode™ LX Processors Data Book 449Video Processor Register Descriptions 33234H6.8.3.38 Even Video Y Position (VYE)6.8.3.39 Even Alpha Window 1 Y

Strany 390

AMD Geode™ LX Processors Data Book 454GeodeLink™ Interface Unit 33234H4.0GeodeLink™ Interface UnitMany traditional architectures use buses to connect

Strany 391

450 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.40 Even Alpha Window 2 Y Position (A2YE) 6.8.3.41 Even Alpha W

Strany 392

AMD Geode™ LX Processors Data Book 451Video Processor Register Descriptions 33234H6.8.3.42 Video Coefficient RAM (VCR) 6.8.3.43 Panel Timing Register

Strany 393 - 6.7.4 Color Space Converter

452 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H29 FP_HSYNC_POLFP_HSYNC Input Polarity. Selects positive or negative

Strany 394 - 6.7.5 Video Overlay

AMD Geode™ LX Processors Data Book 453Video Processor Register Descriptions 33234H6.8.3.44 Panel Timing Register 2 (PT2)VP Memory Offset 408hTyp e R

Strany 395

454 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.45 Power Management (PM)19 MCS Color/Mono Select. Selects colo

Strany 396 - Use video value

AMD Geode™ LX Processors Data Book 455Video Processor Register Descriptions 33234H25 D Display Off Control Source. Selects how DISPEN is controlled.

Strany 397

456 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.46 Dither and Frame Rate Control (DFC)VP Memory Offset 418hTyp

Strany 398 - 6.7.6 Video Output Port

AMD Geode™ LX Processors Data Book 457Video Processor Register Descriptions 33234H6.8.3.47 Dither RAM Control and Address (DCA) 0DENB Dithering Enabl

Strany 399

458 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H6.8.3.48 Dither Memory Data (DMD)6.8.3.49 Panel CRC Signature (CRC)

Strany 400

AMD Geode™ LX Processors Data Book 459Video Processor Register Descriptions 33234H6.8.3.50 32-Bit Panel CRC (CRC32)6.8.3.51 Video Output Port Configu

Strany 401 - Table 6-61. VOP Mode

46 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Unit33234H4.1.1 Port AddressEach GLIU has seven channels with Channel 0 being theGLIU itsel

Strany 402 - Table 6-62. SAV/EAV Sequence

460 AMD Geode™ LX Processors Data Book Video Processor Register Descriptions33234H18 INV VS POL Invert VSYNC Polarity. Set to 1 to invert polarity of

Strany 403

AMD Geode™ LX Processors Data Book 461Video Processor Register Descriptions 33234H6.8.3.52 Video Output Port Signature (VOP_SIG)6 SC120X_MODE SC120X

Strany 404 - Table 6-65. VOP Clock Rate

462 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9 Video Input Port6.9.1 Features• VESA 1.1, 2.0 and BT.601, BT.656 compliant, 150 MHz (

Strany 405

AMD Geode™ LX Processors Data Book 463Video Input Port 33234H6.9.2 VIP Block DescriptionsFigure 6-39. VIP Block Diagram8/16Addressaddress FormatterGe

Strany 406

464 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9.2.1 Input FormatterThe Input Formatter receives 8- or 16-bit VIP input data, Itdoes a

Strany 407

AMD Geode™ LX Processors Data Book 465Video Input Port 33234H6.9.3 Functional DescriptionThe Video Input Port (VIP) receives 8- or 16-bit video oranc

Strany 408

466 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9.5 Mode 1a,b,c - VIP Input Data (simplified BT.656)The VIP 2.0 specification describes

Strany 409

AMD Geode™ LX Processors Data Book 467Video Input Port 33234HVIP 2.0 Video FlagsTwo new video flags are defined in the VIP 2.0 specificationto decode

Strany 410 - Disable Feature

468 AMD Geode™ LX Processors Data Book Video Input Port33234HFigure 6-41. 525 line, 60 Hz Digital Vertical TimingLine 1 (V = 1)Line 20(V = 0)Line 264

Strany 411 - Table 6-68. Display RGB Modes

AMD Geode™ LX Processors Data Book 469Video Input Port 33234H6.9.5.2 Ancillary PacketsAncillary packets are received during vertical and/or hori-zont

Strany 412

AMD Geode™ LX Processors Data Book 47GeodeLink™ Interface Unit 33234H4.1.2 Port Addressing ExceptionsThere are some exceptions to the port addressing

Strany 413

470 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9.6 Message Passing ModeThe Message Passing mode (MSG) allows an externaldevice to pass

Strany 414

AMD Geode™ LX Processors Data Book 471Video Input Port 33234H6.9.8 BT.601 ModeBT.601 mode allows reception of 8- or 16-bit video inputwhich consists

Strany 415

472 AMD Geode™ LX Processors Data Book Video Input Port33234H. Figure 6-46. BT.601 Mode Programmable Field DetectionFigure 6-47. BT.601 Mode Horizonta

Strany 416

AMD Geode™ LX Processors Data Book 473Video Input Port 33234HFigure 6-48. BT.601 Mode Vertical Timing6.9.9 YUV 4:2:2 to YUV 4:2:0 TranslationThe VIP

Strany 417

474 AMD Geode™ LX Processors Data Book Video Input Port33234HFigure 6-49. YUV 4:2:2 to YUV 4:2:0 Translation12463571246357YUV 4:2:2 YUV 4:2:0123 45612

Strany 418

AMD Geode™ LX Processors Data Book 475Video Input Port 33234H6.9.10 Software ModelThe VIP receives data and stores it into system memory.The VIP inpu

Strany 419 - MSR_DIAG_VP Bit Descriptions

476 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9.10.1 Video Data BuffersVideo data buffers can be organized in linear or planar for-ma

Strany 420 - MSR_PADSEL Bit Descriptions

AMD Geode™ LX Processors Data Book 477Video Input Port 33234HFigure 6-51. Example VIP YUV 4:2:2 SAV/EAV Packets Stored in System Memory in a Linear B

Strany 421 - VCFG Bit Descriptions

478 AMD Geode™ LX Processors Data Book Video Input Port33234HFigure 6-52. Example VIP YUV 4:2:0 Planar Buffer (all base registers are 8-byte aligned)U

Strany 422 - DCFG Register Map

AMD Geode™ LX Processors Data Book 479Video Input Port 33234HFigure 6-53. Example VIP 8/16- and 10-bit Ancillary Packets Stored in System Memory0123(

Strany 423 - DCFG Bit Descriptions

48 AMD Geode™ LX Processors Data Book GeodeLink™ Interface Unit33234HEach memory request is compared against all the P2Ddescriptors. If the memory req

Strany 424 - VX Bit Descriptions

480 AMD Geode™ LX Processors Data Book Video Input Port33234H6.9.11 Bob and WeaveBob and Weave are two methods of outputting interlacedvideo, captured

Strany 425 - SCL Bit Descriptions

AMD Geode™ LX Processors Data Book 481Video Input Port 33234HVertical Timing Error (Frame or Address Error) /Mes-sage Missed Error - This error indic

Strany 426 - VCK Bit Descriptions

482 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10 Video Input Port Register DescriptionsThe registers associated

Strany 427 - VCM Bit Descriptions

AMD Geode™ LX Processors Data Book 483Video Input Port Register Descriptions 33234H44h R/W VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BASE

Strany 428 - PDR Bit Descriptions

484 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.1 Standard GeodeLink™ Device (GLD) MSRs6.10.1.1 GLD Capabiliti

Strany 429 - SLR Bit Descriptions

AMD Geode™ LX Processors Data Book 485Video Input Port Register Descriptions 33234H6.10.1.3 GLD SMI MSR (GLD_MSR_SMI)MSR Address 54002002hTyp e R /WR

Strany 430 - MISC Bit Descriptions

486 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.1.4 GLD Error MSR (GLD_MSR_ERROR)MSR Address 54002003hTyp e R

Strany 431 - VXS Register Map

AMD Geode™ LX Processors Data Book 487Video Input Port Register Descriptions 33234H6.10.1.5 GLD Power Management Register (GLD_MSR_PM)6.10.1.6 GLD Di

Strany 432 - VDC Bit Descriptions

488 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2 VIP Control/Configuration Registers6.10.2.1 VIP Control Regi

Strany 433 - CRC Bit Descriptions

AMD Geode™ LX Processors Data Book 489Video Input Port Register Descriptions 33234H19 NI Non-Interlaced Video Input. This bit determines if the start

Strany 434 - VDE Bit Descriptions

AMD Geode™ LX Processors Data Book 49GeodeLink™ Interface Unit 33234H4.1.3.2 I/O Routing and TranslationI/O addresses are routed and are never transl

Strany 435

490 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.2 VIP Control Register 2 (VIP_CTL_REG2)3:1 VIP_MODE VIP Oper

Strany 436 - CCK Bit Descriptions

AMD Geode™ LX Processors Data Book 491Video Input Port Register Descriptions 33234H26 ANCPEN Ancillary Parity Check Enable. When set to 1, ancillary

Strany 437 - CC1 Bit Descriptions

492 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.3 VIP Status (VIP_STATUS)VIP Memory Offset 08hTyp e R /WRese

Strany 438 - A1X Bit Descriptions

AMD Geode™ LX Processors Data Book 493Video Input Port Register Descriptions 33234H14 MSG_BERR Message Buffer Error.0: No error.1: Message buffer was

Strany 439 - A1C Register Map

494 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.4 VIP Interrupt (VIP_INT)VIP Memory Offset 0ChTyp e R /WRese

Strany 440 - A1T Register Map

AMD Geode™ LX Processors Data Book 495Video Input Port Register Descriptions 33234H6.10.2.5 VIP Current/Target (VIP_CUR_TAR)6.10.2.6 VIP Max Address

Strany 441 - A2X Bit Descriptions

496 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.7 VIP Task A Video Even Base Address (VIP_TASK_A_VID_EVEN_BA

Strany 442 - A2C Register Map

AMD Geode™ LX Processors Data Book 497Video Input Port Register Descriptions 33234H6.10.2.9 VIP Task A VBI Even Base Address (VIP_TASK_A_VBI_EVEN_BAS

Strany 443 - A2T Bit Descriptions

498 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.11 VIP Task A Video Pitch (VIP_TASK_A_VID_PITCH)6.10.2.12 VI

Strany 444 - A3X Bit Descriptions

AMD Geode™ LX Processors Data Book 499Video Input Port Register Descriptions 33234H6.10.2.13 VIP Task A V Offset (VIP_TASK_A_V_OFFSET) 7EFD Even Fiel

Strany 445 - A3C Register Map

AMD Geode™ LX Processors Data Book 5List of Figures 33234HList of FiguresFigure 1-1. Internal Block Diagram . . . . . . . . . . . . . . . . . . . . .

Strany 446 - A3T Bit Descriptions

50 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2 GLIU Register DescriptionsAll GeodeLink™ Interface Unit (GLIU) registers are

Strany 447 - VRR Bit Descriptions

500 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.14 VIP Task A U Offset (VIP_TASK_A_U_OFFSET)6.10.2.15 VIP Ta

Strany 448 - VTM Bit Descriptions

AMD Geode™ LX Processors Data Book 501Video Input Port Register Descriptions 33234H6.10.2.16 VIP Task B Video Odd Base/Horizontal Start (VIP_TASK_B_V

Strany 449 - A1YE Bit Descriptions

502 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.18 VIP Task B VBI Odd Base/VBI Start (VIP_TASK_B_VBI_ODD_BAS

Strany 450 - A3YE Bit Descriptions

AMD Geode™ LX Processors Data Book 503Video Input Port Register Descriptions 33234H6.10.2.20 VIP Task B V Offset (VIP_TASK_B_V_Offset) 27:16 VERTICAL

Strany 451 - PT1 Bit Descriptions

504 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.21 VIP Task B U Offset (VIP_TASK_B_U_OFFSET)6.10.2.22 VIP An

Strany 452

AMD Geode™ LX Processors Data Book 505Video Input Port Register Descriptions 33234H6.10.2.23 VIP Ancillary Data/Message Passing/Data Streaming Buffer

Strany 453 - PT2 Bit Descriptions

506 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.25 VIP Page Offset/ Page Count (VIP_PAGE_OFFSET) 6.10.2.26 V

Strany 454 - PM Bit Descriptions

AMD Geode™ LX Processors Data Book 507Video Input Port Register Descriptions 33234H6.10.2.27 VIP FIFO Address (VIP_FIFO_R_W_ADDR)6.10.2.28 VIP FIFO D

Strany 455

508 AMD Geode™ LX Processors Data Book Video Input Port Register Descriptions33234H6.10.2.29 VIP VSYNC Error Count (VIP_SYNC_ERR_COUNT)6.10.2.30 VIP T

Strany 456 - DFC Bit Descriptions

AMD Geode™ LX Processors Data Book 509Video Input Port Register Descriptions 33234H6.10.2.31 VIP Task A V Even Offset (VIP_TASK_A_V_EVEN_OFFSET) VIP

Strany 457 - DCA Bit Descriptions

AMD Geode™ LX Processors Data Book 51GLIU Register Descriptions 33234HGLIU0: 10000089h GLIU1: 40000089hRO SLAVE_ONLY GLIU0: 00000000_00000010h GLIU1:

Strany 458 - DMD Bit Descriptions

510 AMD Geode™ LX Processors Data Book Security Block33234H6.11 Security BlockThe Security Block provides a hardware Advanced Encryp-tion Standard (AE

Strany 459 - Bit Descriptions

AMD Geode™ LX Processors Data Book 511Security Block 33234H6.11.2 Functional DescriptionThe AES engine provides ECB and CBC 128-bit hardwareencryptio

Strany 460 - Bit Descriptions (Continued)

512 AMD Geode™ LX Processors Data Book Security Block33234H6.11.2.1 EEPROM ID InterfaceThe EEPROM ID interface provides an interface to anEEPROM non-v

Strany 461

AMD Geode™ LX Processors Data Book 513Security Block Register Descriptions 33234H6.12 Security Block Register DescriptionsThis section provides infor

Strany 462 - 6.9 Video Input Port

514 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H048h R/W SB CBC Initialization Vector 2 (SB_CBC_IV_2)00000000h Page 5

Strany 463 - 6.9.2 VIP Block Descriptions

AMD Geode™ LX Processors Data Book 515Security Block Register Descriptions 33234H6.12.1 Standard GeodeLink™ (GLD) Device MSRs6.12.1.1 GLD Capabilitie

Strany 464 - Video Input Port

516 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.1.3 GLD SMI MSR (GLD_MSR_SMI)6.12.1.4 GLD Error MSR (GLD_MSR_ERR

Strany 465 - 6.9.4 VIP Operation Modes

AMD Geode™ LX Processors Data Book 517Security Block Register Descriptions 33234HGLD_MSR_ERROR Register Map63 62 61 60 59 58 57 56 55 54 53 52 51 50

Strany 466 - Table 6-73. SAV/EAV Sequence

518 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.1.5 GLD Power Management MSR (GLD_MSR_PM)6.12.1.6 GLD Diagnostic

Strany 467

AMD Geode™ LX Processors Data Book 519Security Block Register Descriptions 33234H6.12.2 Security Block Specific MSRs6.12.2.1 GLD Control MSR (GLD_MSR

Strany 468

52 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234HGLIU0: 100000C0h GLIU1: 400000C0hR/W Request Compare Value (RQ_COMPARE_VAL[0])00

Strany 469

520 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3 Security Block Configuration/Control Registers6.12.3.1 SB Cont

Strany 470 - 6.9.7 Data Streaming Mode

AMD Geode™ LX Processors Data Book 521Security Block Register Descriptions 33234H6.12.3.2 SB Control B (SB_CTL_B)0STA Start for A Pointer. When set,

Strany 471 - 6.9.8 BT.601 Mode

522 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.3 SB AES Interrupt (SB_AES_INT)6.12.3.4 SB Source A (SB_SOURCE

Strany 472

AMD Geode™ LX Processors Data Book 523Security Block Register Descriptions 33234H6.12.3.5 SB Destination A (SB_DEST_A)6.12.3.6 SB Length A (SB_LENGTH

Strany 473

524 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.7 SB Source B (SB_SOURCE_B)6.12.3.8 SB Destination B (SB_DEST_

Strany 474

AMD Geode™ LX Processors Data Book 525Security Block Register Descriptions 33234H6.12.3.9 SB Length B (SB_LENGTH_B)6.12.3.10 SB Writable Key 0 (SB_WK

Strany 475 - 6.9.10 Software Model

526 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.11 SB Writable Key 1 (SB_WKEY_1)6.12.3.12 SB Writable Key 2 (S

Strany 476

AMD Geode™ LX Processors Data Book 527Security Block Register Descriptions 33234H6.12.3.13 SB Writable Key 3 (SB_WKEY_3)6.12.3.14 SB CBC Initializati

Strany 477

528 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.15 SB CBC Initialization Vector 1 (SB_CBC_IV_1)6.12.3.16 SB CB

Strany 478

AMD Geode™ LX Processors Data Book 529Security Block Register Descriptions 33234H6.12.3.18 SB Random Number (SB_RANDOM_NUM)6.12.3.19 SB Random Number

Strany 479

AMD Geode™ LX Processors Data Book 53GLIU Register Descriptions 33234HGLIU0: 100000DEh GLIU1: 400000DEhR/W Data Compare Mask Low (DA_COMPARE_MASK_LO[

Strany 480 - 6.9.12 VIP Interrupts

530 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.20 SB EEPROM Command (SB_EEPROM_COMM)SB Memory Offset 800hTyp

Strany 481 - 6.9.13 VIP Input Video Status

AMD Geode™ LX Processors Data Book 531Security Block Register Descriptions 33234H6.12.3.21 SB EEPROM Address (SB_EEPROM_ADDR)6.12.3.22 SB EEPROM Data

Strany 482

532 AMD Geode™ LX Processors Data Book Security Block Register Descriptions33234H6.12.3.23 SB EEPROM Security State (SB_EEPROM_SEC_STATE)This read onl

Strany 483

AMD Geode™ LX Processors Data Book 533GeodeLink™ Control Processor 33234H6.13 GeodeLink™ Control ProcessorThe GeodeLink Control Processor (GLCP) func

Strany 484

534 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor33234H Table 6-81. TAP Control Instructions (25-Bit IR)InstructionDRLength IR Name

Strany 485

AMD Geode™ LX Processors Data Book 535GeodeLink™ Control Processor 33234HEXTEST JTAG InstructionThe EXTEST instruction accesses the boundary scanchai

Strany 486

536 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor33234HFigure 6-56. Processor Clock Generation6.13.4 Companion Device InterfaceThe A

Strany 487

AMD Geode™ LX Processors Data Book 537GeodeLink™ Control Processor 33234HFigure 6-57. GIO Interface Block DiagramGIO_GLIUGIO_SYNCGIO_PCIGIO_A20MGIO_N

Strany 488 - VIP_CTL_REG1 Bit Descriptions

538 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor33234HGIO_PCI Serial ProtocolThe GIO can override the functionality of its SUSP# pi

Strany 489

AMD Geode™ LX Processors Data Book 539GeodeLink™ Control Processor Register Descriptions 33234H6.14 GeodeLink™ Control Processor Register Description

Strany 490 - VIP_CTL_REG2 Bit Descriptions

54 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234HTable 4-10. GLIU IOD Descriptor MSRs Summary MSR Address Type Register Reset Va

Strany 491 - 100-111: 0

540 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H4C000015h R/W GLCP Dot Clock PLL Control (GLCP_DOTPLL)0

Strany 492 - VIP_STATUS Bit Descriptions

AMD Geode™ LX Processors Data Book 541GeodeLink™ Control Processor Register Descriptions 33234H6.14.1 Standard GeodeLink™ Device MSRs6.14.1.1 GLD Cap

Strany 493

542 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.1.3 GLD SMI MSR (GLD_MSR_SMI)MSR Address 4C002002h

Strany 494 - VIP_INT Bit Descriptions

AMD Geode™ LX Processors Data Book 543GeodeLink™ Control Processor Register Descriptions 33234H6.14.1.4 GLD Error MSR (GLD_MSR_ERROR)MSR Address 4C00

Strany 495 - VIP_MAX_ADDR Bit Descriptions

544 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.1.5 GLD Power Management MSR (GLD_MSR_PM)The debug

Strany 496

AMD Geode™ LX Processors Data Book 545GeodeLink™ Control Processor Register Descriptions 33234H6.14.2 GLCP Specific MSRs - GLCP Control MSRs6.14.2.1

Strany 497

546 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H28 GLCPDBG GLCP Debug Clock Off. When set, disables GLC

Strany 498 - VIP_CONTRL_REG3 Register Map

AMD Geode™ LX Processors Data Book 547GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.3 Chip Fabrication Information (GLCP_FAB) This

Strany 499 - even lines will also

548 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.2.5 GLCP Debug Output from Chip (GLCP_DBGOUT)This

Strany 500

AMD Geode™ LX Processors Data Book 549GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.7 GLCP DOWSER (GLCP_DOWSER)6.14.2.8 GLCP I/O De

Strany 501

AMD Geode™ LX Processors Data Book 55GLIU Register Descriptions 33234H4.2.1 Standard GeodeLink™ Device (GLD) MSRs4.2.1.1 GLD Capabilities MSR (GLD_MS

Strany 502

550 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H59 SDCLK_SET SDCLK Setup.0: Full SDCLK setup.1: Half SD

Strany 503 - TASK_B_V_OFFSET_START_ODD

AMD Geode™ LX Processors Data Book 551GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.9 GLCP Clock Control (GLCP_CLKOFF)This register

Strany 504 - TASK_B_U_OFFSET)

552 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.2.10 GLCP Clock Active (GLCP_CLKACTIVE)See "G

Strany 505 - VIP_ANC_MSG_SIZE Register Map

AMD Geode™ LX Processors Data Book 553GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.11 GLCP Clock Mask for Debug Clock Stop Action

Strany 506

554 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.2.13 GLCP System Reset and PLL Control (GLCP_SYS_R

Strany 507 - VIP_FIFO_DATA Register Map

AMD Geode™ LX Processors Data Book 555GeodeLink™ Control Processor Register Descriptions 33234H23:16 HOLD_COUNT Hold Count. The number of PLL referen

Strany 508

556 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234HThe PW1 pin (66 MHz PCI) is wired directly to the CORED

Strany 509

AMD Geode™ LX Processors Data Book 557GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.14 GLCP Dot Clock PLL Control (GLCP_DOTPLL)This

Strany 510 - 6.11 Security Block

558 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234HGLCP_DOTPLL Bit DescriptionsBit Name Description63:49 R

Strany 511 - 6.11.2 Functional Description

AMD Geode™ LX Processors Data Book 559GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.15 GLCP Debug Clock Control (GLCP_DBGCLKCTL)Not

Strany 512 - Security Block

56 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.1.3 GLD SMI MSR (GLD_MSR_SMI) The flags are set with internal conditions. Th

Strany 513

560 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.2.17 GLCP Control (GLCP_CNT)This register is used

Strany 514

AMD Geode™ LX Processors Data Book 561GeodeLink™ Control Processor Register Descriptions 33234H6.14.2.19 GLCP Throttle or C2 Start Delay (GLCP_TH_SD)

Strany 515

562 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.2.21 GLCP Processor Throttle Off Delay (GLCP_TH_OD

Strany 516

AMD Geode™ LX Processors Data Book 563GeodeLink™ Control Processor Register Descriptions 33234H6.14.4 GLCP Specific MSRs - GLCP Debug Interface MSRs6

Strany 517

564 AMD Geode™ LX Processors Data Book GeodeLink™ Control Processor Register Descriptions33234H6.14.5 GLCP Specific MSRs - GLCP Companion Device Inter

Strany 518

AMD Geode™ LX Processors Data Book 565GeodeLink™ Control Processor Register Descriptions 33234H6.14.5.3 GLIU Device Interrupt Status (MSR_INTAX)This

Strany 519 - GLD_MSR_CTRL Bit Descriptions

566 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge33234H6.15 GeodeLink™ PCI BridgeThe GeodeLink™ PCI Bridge (GLPCI) module provides aPCI int

Strany 520 - SB_CTL_A Register Map

AMD Geode™ LX Processors Data Book 567GeodeLink™ PCI Bridge 33234H6.15.1 GeodeLink™ Interface BlockThe GeodeLink Interface block provides a thin prot

Strany 521 - SB_CTL_B Register Map

568 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge33234HFigure 6-59. Atomic MSR Accesses Across the PCI BusGLIU1Device-A Device-BDevice-CPCI

Strany 522 - SB_SOURCE_A Register Map

AMD Geode™ LX Processors Data Book 569GeodeLink™ PCI Bridge 33234H6.15.4 PCI Bus Interface BlockThe PCI Bus Interface block is compliant to the PCI 2

Strany 523 - SB_LENGTH_A Register Map

AMD Geode™ LX Processors Data Book 57GLIU Register Descriptions 33234H4.2.1.4 GLD Error MSR (GLD_MSR_ERROR)The flags are set with internal conditions

Strany 524 - SB_DEST_B Register Map

570 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge33234H6.15.5 PCI ArbiterThe PCI arbiter implements a fair arbitration scheme withspecial s

Strany 525 - SB_LENGTH_B Register Map

AMD Geode™ LX Processors Data Book 571GeodeLink™ PCI Bridge 33234H6.15.6 Exception Handling6.15.6.1 Out-Bound Write ExceptionsWhen performing an out-

Strany 526 - SB_WKEY_2 Bit Descriptions

572 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16 GeodeLink™ PCI Bridge Register DescriptionsAll GeodeLink™

Strany 527 - SB_CBC_IV_0 Bit Descriptions

AMD Geode™ LX Processors Data Book 573GeodeLink™ PCI Bridge Register Descriptions 33234H5000201Dh R/W GLPCI Memory Region 5 Configuration (GLPCI_R5)0

Strany 528

574 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.1 Standard GeodeLink™ Device (GLD) MSRs6.16.1.1 GLD Capab

Strany 529 - SB_RANDOM_NUM Register Map

AMD Geode™ LX Processors Data Book 575GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.1.3 GLD SMI MSR (GLD_MSR_SMI) MSR Address 50002002hTyp e

Strany 530 - SB_EEPROM_COMM Register Map

576 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.1.4 GLD Error MSR (GLD_MSR_ERROR)MSR Address 50002003hTyp

Strany 531 - SB_EEPROM_DATA Register Map

AMD Geode™ LX Processors Data Book 577GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.1.5 GLD Power Management MSR (GLD_MSR_PM)6.16.1.6 GLD Di

Strany 532

578 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2 GLPCI Specific Registers6.16.2.1 GLPCI Global Control (

Strany 533 - 6.13.1 TAP Controller

AMD Geode™ LX Processors Data Book 579GeodeLink™ PCI Bridge Register Descriptions 33234H42 SLTO Subsequent Latency Timeout Select. Specifies the subs

Strany 534 - GeodeLink™ Control Processor

58 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H39 EFLAG7 Request Comparator Error Flag 0. If high, records that an ERR was gene

Strany 535 - 6.13.3 Clock Control

580 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H24 MARS Master Abort Receive ASMI. Allow reception of a PCI bu

Strany 536

AMD Geode™ LX Processors Data Book 581GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.2 GLPCI Arbiter Control (GLPCI_ARB)9LDE Latency Discon

Strany 537 - Table 6-83. GIO_PCI Outputs

582 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234HGLPCI_ARB Bit DefinitionsBit Name Description63:60 CR CPU Repe

Strany 538

AMD Geode™ LX Processors Data Book 583GeodeLink™ PCI Bridge Register Descriptions 33234H20 OV0 Override 0. Enables requester0 to override the repeat-

Strany 539

584 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.3 GLPCI VPH / PCI Configuration Cycle Control (GLPCI_PB

Strany 540

AMD Geode™ LX Processors Data Book 585GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.6 GLPCI Fixed Region Configuration A0-BF (GLPCI_A0)GLP

Strany 541

586 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.7 GLPCI Fixed Region Configuration C0-DF (GLPCI_C0)GLPC

Strany 542

AMD Geode™ LX Processors Data Book 587GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.8 GLPCI Fixed Region Configuration E0-FF (GLPCI_E0)39:

Strany 543

588 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.9 GLPCI Memory Region 0 Configuration (GLPCI_R0)MSR Add

Strany 544

AMD Geode™ LX Processors Data Book 589GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.10 GLPCI Memory Region 1 Configuration (GLPCI_R1)MSR A

Strany 545

AMD Geode™ LX Processors Data Book 59GLIU Register Descriptions 33234H4.2.1.5 GLD Power Management MSR (GLD_MSR_PM)8 EMASK8 Request Comparator Error

Strany 546

590 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.11 GLPCI Memory Region 2 Configuration (GLPCI_R2)MSR Ad

Strany 547 - GLCP_GLB_PM Bit Descriptions

AMD Geode™ LX Processors Data Book 591GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.12 GLCPI Memory Region 3 Configuration (GLPCI_R3)MSR A

Strany 548 - GLCP_PROCSTAT Register Map

592 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.13 GLCPI Memory Region 4 Configuration (GLPCI_R4)MSR Ad

Strany 549 - GLCP_DOWSER Bit Descriptions

AMD Geode™ LX Processors Data Book 593GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.14 GLPCI Memory Region 5 Configuration (GLPCI_R5)MSR A

Strany 550

594 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.15 GLPCI External MSR Access Configuration (GLPCI EXT_M

Strany 551 - GLCP_CLKOFF Bit Descriptions

AMD Geode™ LX Processors Data Book 595GeodeLink™ PCI Bridge Register Descriptions 33234H6.16.2.16 GLPCI SpareMSR Address 5000201FhTyp e R /WReset Val

Strany 552 - GLCP_CLKACTIVE Register Map

596 AMD Geode™ LX Processors Data Book GeodeLink™ PCI Bridge Register Descriptions33234H6.16.2.17 GLPCI General Purpose I/O (GLPCI_GPIO)MSR Address 50

Strany 553 - GLCP_CLK4ACK Register Map

AMD Geode™ LX Processors Data Book 5977Electrical Specifications 33234H7.0Electrical SpecificationsThis section provides information on electrical co

Strany 554 - GLCP_SYS_RSTPLL Register Map

598 AMD Geode™ LX Processors Data Book Electrical Specifications33234H7.3 Operating ConditionsTable 7-2 lists the operating conditions for the AMD Geo

Strany 555

AMD Geode™ LX Processors Data Book 599Electrical Specifications 33234H7.4 DC CurrentDC current is not a simple measurement. Three of theAMD Geode LX

Strany 556

6 AMD Geode™ LX Processors Data Book List of Figures33234HFigure 6-42. Ancillary Data Packets . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Strany 557 - GLCP_DOTPLL Register Map

60 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.1.6 GLD Diagnostic MSR (GLD_MSR_DIAG)This register is reserved for internal

Strany 558 - GLCP_DOTPLL Bit Descriptions

600 AMD Geode™ LX Processors Data Book Electrical Specifications33234HThe data bus on the DDR SDRAM has a low voltage swingwhen actively terminated (t

Strany 559 - GLCP_CHIP_REVID Register Map

AMD Geode™ LX Processors Data Book 601Electrical Specifications 33234HTable 7-4. AMD Geode LX [email protected] Processor DC CurrentsLX [email protected] (500 MHz), No

Strany 560 - GLCP_CNT Bit Descriptions

602 AMD Geode™ LX Processors Data Book Electrical Specifications33234HTable 7-5. AMD Geode LX [email protected] Processor DC CurrentsLX [email protected] (433 MHz), No

Strany 561 - GLCP_TH_SF Bit Descriptions

AMD Geode™ LX Processors Data Book 603Electrical Specifications 33234HTable 7-6. AMD Geode LX [email protected] Processor DC CurrentsLX [email protected] (366 MHz), No

Strany 562 - GLCP_TH_OD Bit Descriptions

604 AMD Geode™ LX Processors Data Book Electrical Specifications33234H7.5 DC CharacteristicsAll DC parameters and current measurements in this section

Strany 563 - GLCP_DAC Bit Descriptions

AMD Geode™ LX Processors Data Book 605Electrical Specifications 33234HILEAKInput Leakage Current Including Hi-Z Output Leakage, Note 1PCI -3.0 3.0 µA

Strany 564 - MSR_INIT Bit Descriptions

606 AMD Geode™ LX Processors Data Book Electrical Specifications33234HIOLOutput Low Current, Note 1 VO = VOL (Max)PCI 1500 µA24/Q3 24.0 mA24/Q5 24.0 m

Strany 565 - MSR_INTAX Bit Descriptions

AMD Geode™ LX Processors Data Book 607Electrical Specifications 33234H7.6 AC CharacteristicsThe following tables list the AC characteristics includin

Strany 566 - 6.15 GeodeLink™ PCI Bridge

608 AMD Geode™ LX Processors Data Book Electrical Specifications33234HFigure 7-3. Drive Level and Measurement Points for Switching CharacteristicsTabl

Strany 567 - GeodeLink™ PCI Bridge

AMD Geode™ LX Processors Data Book 609Electrical Specifications 33234HFigure 7-4. Power Up SequencingFigure 7-5. Drive Level and Measurement Points f

Strany 568 - AMD Geode™ LX Processor

AMD Geode™ LX Processors Data Book 61GLIU Register Descriptions 33234H4.2.2.2 Port Active Enable (PAE)Ports that are not implemented return 00 (RSVD)

Strany 569

610 AMD Geode™ LX Processors Data Book Electrical Specifications33234HFigure 7-6. Drive Level and Measurement Points for Switching CharacteristicsTabl

Strany 570

AMD Geode™ LX Processors Data Book 611Electrical Specifications 33234HFigure 7-7. Drive Level and Measurement Points for Switching CharacteristicsTab

Strany 571 - 6.15.6 Exception Handling

612 AMD Geode™ LX Processors Data Book Electrical Specifications33234HTable 7-12. CRT Interface Signals Symbol Parameter Min Max Unit CommentstCKDOTCL

Strany 572

AMD Geode™ LX Processors Data Book 613Electrical Specifications 33234HTable 7-14. CRT Display Analog (DAC) CharacteristicsSymbol Parameter Min Typ Ma

Strany 573

614 AMD Geode™ LX Processors Data Book Electrical Specifications33234HTable 7-15. Memory (DDR) Interface Signals Symbol(Note 1) Parameter Min Max Unit

Strany 574

AMD Geode™ LX Processors Data Book 615Electrical Specifications 33234HFigure 7-8. DDR Write Timing Measurement PointsSDCLK[5:1]PNon-DQ OutputsVREFVal

Strany 575

616 AMD Geode™ LX Processors Data Book Electrical Specifications33234HFigure 7-9. DDR Read Timing Measurement PointsDQ InputsVREFDQtVREFDQt-1SDCLK0DQS

Strany 576

AMD Geode™ LX Processors Data Book 617Electrical Specifications 33234H Table 7-16. JTAG Interface Signals Symbol Parameter Min Max Unit CommentsTCLK

Strany 577

618 AMD Geode™ LX Processors Data Book Electrical Specifications33234H

Strany 578 - GLPCI_CTRL Bit Descriptions

AMD Geode™ LX Processors Data Book 6198Instruction Set 33234H8.0Instruction SetThis chapter provides the general instruction set format and detailed i

Strany 579

62 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.2.3 Arbitration (ARB)4.2.2.4 Asynchronous SMI (ASMI)ASMI is a condensed vers

Strany 580

620 AMD Geode™ LX Processors Data BookInstruction Set33234H8.1.1 Prefix (Optional) Prefix bytes can be placed in front of any instruction to modify th

Strany 581 - GLPCI_ARB Register Map

AMD Geode™ LX Processors Data Book 621Instruction Set 33234H8.1.2 OpcodeThe opcode field specifies the operation to be performed by the instruction. T

Strany 582 - GLPCI_ARB Bit Definitions

622 AMD Geode™ LX Processors Data BookInstruction Set33234H8.1.2.4 eee Field (MOV-Instruction Register Selection)The eee field (bits [5:3]) is used to

Strany 583

AMD Geode™ LX Processors Data Book 623Instruction Set 33234H01 000 DS:[BX+SI+d8] DS:[EAX+d8]01 001 DS:[BX+DI+d8] DS:[ECX+d8]01 010 SS:[BP+SI+d8] DS:[E

Strany 584 - GLPCI_REN Register Map

624 AMD Geode™ LX Processors Data BookInstruction Set33234H8.1.4 reg FieldThe reg field (Table 8-10) determines which general registers are to be used

Strany 585 - GLPCI_A0 Register Map

AMD Geode™ LX Processors Data Book 625Instruction Set 33234H8.1.5 s-i-b Byte (Scale, Indexing, Base)The s-i-b fields provide scale factor, indexing, a

Strany 586 - GLPCI_C0 Bit Descriptions

626 AMD Geode™ LX Processors Data BookInstruction Set33234H8.1.5.3 Base Field (s-i-b Present)In Table 8-8 on page 622, the note “s-i-b is present” for

Strany 587 - GLPCI_E0 Bit Descriptions

AMD Geode™ LX Processors Data Book 627Instruction Set 33234H8.2 CPUID Instruction SetThe CPUID instruction (opcode 0FA2) allows software to make proce

Strany 588 - GLPCI_R0 Bit Descriptions

628 AMD Geode™ LX Processors Data BookInstruction Set33234HTable 8-18. CPUID Instruction Codes with EAX = 00000000RegisterResetValue Description Comme

Strany 589 - GLPCI_R1 Bit Descriptions

AMD Geode™ LX Processors Data Book 629Instruction Set 33234H8.2.2 Extended CPUID LevelsTesting for extended CPUID instruction support can be accomplis

Strany 590 - GLPCI_R2 Bit Descriptions

AMD Geode™ LX Processors Data Book 63GLIU Register Descriptions 33234H4.2.2.5 Asynchronous ERR (AERR)AERR is a condensed version of the port ERR sign

Strany 591 - GLPCI_R3 Bit Descriptions

630 AMD Geode™ LX Processors Data BookInstruction Set33234HTable 8-21. CPUID Instruction Codes with EAX = 80000001hRegister Reset Value Description Co

Strany 592 - GLPCI_R4 Bit Descriptions

AMD Geode™ LX Processors Data Book 631Instruction Set 33234H8.2.2.3 CPUID Instruction with EAX = 80000002h, 80000003h, or 80000004hExtended functions

Strany 593 - GLPCI_R5 Bit Descriptions

632 AMD Geode™ LX Processors Data BookInstruction Set33234H8.2.2.4 CPUID Instruction with EAX = 80000005hExtended function 80000005h (EAX = 80000005h)

Strany 594 - GLPCI_EXT_MSR Register Map

AMD Geode™ LX Processors Data Book 633Instruction Set 33234H8.3 Processor Core Instruction SetThe instruction set for the AMD Geode LX processor core

Strany 595 - GLPCI Spare Bit Descriptions

634 AMD Geode™ LX Processors Data BookInstruction Set33234HTable 8-26. Processor Core Instruction Set Instruction OpcodeClock Count (Reg/Cache Hit) Fl

Strany 596 - GLPCI_GPIO Register Map

AMD Geode™ LX Processors Data Book 635Instruction Set 33234HBTS Test Bit and Set --------x b hRegister/Memory, Immediate 0F BA [mod 101 r/m] # 2 2Regi

Strany 597 - 7.0Electrical Specifications

636 AMD Geode™ LX Processors Data BookInstruction Set33234HCMOVNS Move if Not Sign 0F 49 [mod reg r/m] 1 1 --------- rRegister, Register/MemoryCMP Com

Strany 598 - 7.3 Operating Conditions

AMD Geode™ LX Processors Data Book 637Instruction Set 33234HIMUL Integer (Signed) Multiply x---xxuux b hAccumulator by Register/MemoryMultiplier: Byte

Strany 599 - 7.4 DC Current

638 AMD Geode™ LX Processors Data BookInstruction Set33234HJNBE/JA Jump on Not Below or Equal/Above -------- r8-bit Displacement 77 + 1 1Full Displace

Strany 600 - Power Split

AMD Geode™ LX Processors Data Book 639Instruction Set 33234HLOOPNZ/LOOPNE Offset E0 + 2 2 --------- rLOOPZ/LOOPE Offset E1 + 2 2 --------- rLSL Load S

Strany 601 - MEMDDR2ON

64 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234HAERR Register Map63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43

Strany 602

640 AMD Geode™ LX Processors Data BookInstruction Set33234HOUT Output to Port --------- mFixed Port E [011w] # 8 8/23Variable Port E [111w] 8 8/23OUTS

Strany 603

AMD Geode™ LX Processors Data Book 641Instruction Set 33234HREP CMPSCX==0 66CX==1 13 13CX>1 10+3C 10+3CREP INS Input String F3 6[110w] --------- b

Strany 604 - 7.5 DC Characteristics

642 AMD Geode™ LX Processors Data BookInstruction Set33234HSAL Shift Left Arithmetic bhRegister/Memory by 1 D[000w] [mod 100 r/m] 1 1 x - - - x x u x

Strany 605

AMD Geode™ LX Processors Data Book 643Instruction Set 33234HSFENCE 11SGDT Store GDT Register b,c hTo Register/Memory 0F 01 [mod 000 r/m] 6 6 ---------

Strany 606

644 AMD Geode™ LX Processors Data BookInstruction Set33234HWRMSR Write to Model Specific Register 0F 30 10 10 ---------XADD Exchange and Add x- - - xx

Strany 607 - 7.6 AC Characteristics

AMD Geode™ LX Processors Data Book 645Instruction Set 33234HInstruction Notes for Instruction Set SummaryNotes a through c apply to real address mode

Strany 608

646 AMD Geode™ LX Processors Data BookInstruction Set33234H8.3.4 Non-Standard Processor Core Instructions8.3.4.1 DMINT - Enter Debug Management ModeOp

Strany 609

AMD Geode™ LX Processors Data Book 647Instruction Set 33234HDescriptionThe DMINT instruction saves portions of the processors state to the Debug Manag

Strany 610

648 AMD Geode™ LX Processors Data BookInstruction Set33234H8.3.4.3 MOV - Move to/from Test RegistersOperationIF (CPL <> 0) THEN#GP(0);ELSEDEST &

Strany 611

AMD Geode™ LX Processors Data Book 649Instruction Set 33234H8.3.4.4 RDM - Leave Debug Management ModeOperationDescriptionThe RDM instruction restores

Strany 612

AMD Geode™ LX Processors Data Book 65GLIU Register Descriptions 33234H4.2.2.6 GLIU Physical Capabilities (PHY_CAP)MSR Address GLIU0: 10000086hGLIU1:

Strany 613

650 AMD Geode™ LX Processors Data BookInstruction Set33234HExceptions#UD If current privilege level is not 0, or the DMM_INST_EN = 0 and if the proces

Strany 614

AMD Geode™ LX Processors Data Book 651Instruction Set 33234H8.3.4.6 RSLDT - Restore Local Descriptor Table Register and DescriptorOperationDescription

Strany 615

652 AMD Geode™ LX Processors Data BookInstruction Set33234H8.3.4.7 RSM - Leave System Management ModeOperationDescriptionThe RSM instruction restores

Strany 616

AMD Geode™ LX Processors Data Book 653Instruction Set 33234HNotesThe RSM instruction does not check the values that it reads from the SMM header for v

Strany 617

654 AMD Geode™ LX Processors Data BookInstruction Set33234HExceptionsNone.NotesNone.8.3.4.10 SMINT - Enter System Management ModeOperationOpcode Instr

Strany 618

AMD Geode™ LX Processors Data Book 655Instruction Set 33234HDescriptionThe SMINT instruction saves portions of the processors state to the System Mana

Strany 619 - 8.0Instruction Set

656 AMD Geode™ LX Processors Data BookInstruction Set33234H8.3.4.12 SVDC - Save Segment Register and DescriptorOperationDescriptionWrite the specified

Strany 620 - Table 8-2. Instruction Fields

AMD Geode™ LX Processors Data Book 657Instruction Set 33234HExceptions#UD If current privilege level is not 0, or the SMM_INST_EN = 0 and if the proce

Strany 621 - Table 8-6. s Field Encoding

658 AMD Geode™ LX Processors Data BookInstruction Set33234H8.4 MMX™, FPU, and AMD 3DNow!™ Technology Instructions SetsThe CPU is functionally divided

Strany 622 - Table 8-7. eee Field Encoding

AMD Geode™ LX Processors Data Book 659Instruction Set 33234Hwindex 1 (imm8) The range given by [index1 (imm8) + 15: index1 (imm8)].windex 2 (imm8) The

Strany 623

66 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.2.7 N Outstanding Response (NOUT_RESP)MSR Address GLIU0: 10000087hGLIU1: 400

Strany 624 - Table 8-10. reg Field

660 AMD Geode™ LX Processors Data BookInstruction Set33234HTable 8-28. MMX™ Instruction Set MMX™ Instructions Opcode Operation Clock Ct NotesEMMS Empt

Strany 625 - Table 8-13. ss Field Encoding

AMD Geode™ LX Processors Data Book 661Instruction Set 33234HPADDUSW Add Unsigned Word with SaturationMMX Register 2 to MMX Register 1 0FDD [11 mm1 mm2

Strany 626 - Instruction Set

662 AMD Geode™ LX Processors Data BookInstruction Set33234HPCMPGTD Pack Compare Greater Than DwordMMX Register 2 to MMX Register 1 0F66 [11 mm1 mm2] M

Strany 627 - 8.2 CPUID Instruction Set

AMD Geode™ LX Processors Data Book 663Instruction Set 33234HPMINSW Packed Minimum Signed WordMMX Register 1with MMX Register 2 0FEA [11 mm1 mm2]MMX re

Strany 628

664 AMD Geode™ LX Processors Data BookInstruction Set33234HPSHUFW Packed Shuffle WordMMX Register1, MMX Register2, imm80F70 [11 mm1 mm2] #MMX reg 1 [w

Strany 629 - 8.2.2 Extended CPUID Levels

AMD Geode™ LX Processors Data Book 665Instruction Set 33234HPSUBB Subtract Byte With Wrap-Around MMX Register 2 to MMX Register 1 0FF8 [11 mm1 mm2]MMX

Strany 630

666 AMD Geode™ LX Processors Data BookInstruction Set33234H1) This instruction must wait for the FPU pipeline to flush. Cycle count depends on what in

Strany 631

AMD Geode™ LX Processors Data Book 667Instruction Set 33234HTable 8-29. FPU Instruction Set FPU Instruction Opcode OperationClock CtSingle/Dbl (or ext

Strany 632

668 AMD Geode™ LX Processors Data BookInstruction Set33234HFDECSTP Decrement Stack pointer D9 F6 Decrement top of stack pointer 1 3FDIV Floating Point

Strany 633 - 8.3.3 Flags

AMD Geode™ LX Processors Data Book 669Instruction Set 33234HFPATAN Function Eval: Tan-1(y/x) D9 F3 ST(1) <--- ATAN[ST(1) / TOS]; then pop TOS 269 -

Strany 634

AMD Geode™ LX Processors Data Book 67GLIU Register Descriptions 33234H4.2.2.8 N Outstanding Write Data (NOUT_WDATA) 4.2.2.9 SLAVE_ONLYMSR Address GLI

Strany 635

670 AMD Geode™ LX Processors Data BookInstruction Set33234HAll references to TOS and ST(n) refer to stack layout prior to execution. Values popped off

Strany 636

AMD Geode™ LX Processors Data Book 671Instruction Set 33234HTable 8-30. AMD 3DNow!™ Technology Instruction SetAMD 3DNow!™ Instructions Opcode/imm8 Ope

Strany 637

672 AMD Geode™ LX Processors Data BookInstruction Set33234HPFMAX Packed Floating-Point MAXimum 2MMX Register1 with MMX Register2 0F0F [11 mm1 mm2] A4M

Strany 638

AMD Geode™ LX Processors Data Book 673Instruction Set 33234H1) These instructions must wait for the FPU pipeline to flush. Cycle count depends on what

Strany 639

674 AMD Geode™ LX Processors Data BookInstruction Set33234H8.4.1 Non-Standard AMD 3DNow!™ Technology Instructions8.4.1.1 PFRCPV - Floating-Point Recip

Strany 640

AMD Geode™ LX Processors Data Book 6759Package Specifications 33234H9.0Package Specifications9.1 Physical DimensionsThe figures in this section provi

Strany 641

676 AMD Geode™ LX Processors Data Book Package Specifications33234HFigure 9-2. BGU481 Bottom View/Dimensions

Strany 642

AAMD Geode™ LX Processors Data Book 677Appendix A: Support Documentation 33234HAppendix ASupport DocumentationA.1 Order InformationOrdering informati

Strany 643

678 AMD Geode™ LX Processors Data Book Appendix A: Order Information33234HTable A-1. Valid OPN CombinationsFamily Architecture MTDPPerformance Indicat

Strany 644

AMD Geode™ LX Processors Data Book 679Appendix A: Data Book Revision History 33234HA.2 Data Book Revision HistoryThis document is a report of the rev

Strany 645

68 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.2.10 WHO AM I (WHOAMI)6 P6_SLAVE_ONLY Port 6 Slave Only. (GLIU0 = Not Used;

Strany 646

One AMD Place • P.O. Box 3453 • Sunnyvale, CA 94088-3453 USA • Tel: 408-749-4000 or 800-538-8450 • TWX: 910-339-9280 • TELEX: 34-6306www.amd.com

Strany 647

AMD Geode™ LX Processors Data Book 69GLIU Register Descriptions 33234H4.2.2.11 GLIU Slave Disable (GLIU_SLV)The slave disable registers are available

Strany 648

AMD Geode™ LX Processors Data Book 7List of Tables 33234HList of TablesTable 2-1. Graphics Processor Feature Comparison . . . . . . . . . . . . . .

Strany 649

70 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.2.12 Arbitration2 (ARB2)MSR Address GLIU0: 1000008DhGLIU1: 4000008DhTyp e R

Strany 650

AMD Geode™ LX Processors Data Book 71GLIU Register Descriptions 33234H4.2.3 GLIU Statistic and Comparator MSRs4.2.3.1 Descriptor Statistic Counter (S

Strany 651

72 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.3.2 Statistic Mask (STATISTIC_MASK[0:3]Descriptor Statistic Mask (STATISTIC_

Strany 652

AMD Geode™ LX Processors Data Book 73GLIU Register Descriptions 33234H4.2.3.3 Statistic Action (STATISTIC_ACTION[0:3]Descriptor Statistic Action (STA

Strany 653

74 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.3.4 Request Compare Value (RQ_COMPARE_VAL[0:3]The RQ Compare Value and the R

Strany 654

AMD Geode™ LX Processors Data Book 75GLIU Register Descriptions 33234H4.2.3.5 Request Compare Mask (RQ_COMPARE_MASK[0:3]The RQ Compare Value and the

Strany 655

76 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.3.6 DA Compare Value Low (DA_COMPARE_VAL_LO[0:3]The DA Compare Value and the

Strany 656

AMD Geode™ LX Processors Data Book 77GLIU Register Descriptions 33234H4.2.3.7 DA Compare Value High (DA_COMPARE_VAL_HI[0:3]The DA Compare Value and t

Strany 657

78 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.3.8 DA Compare Mask Low (DA_COMPARE_MASK_LO[0:3])Data Compare Mask Low (DA_C

Strany 658

AMD Geode™ LX Processors Data Book 79GLIU Register Descriptions 33234H4.2.3.9 DA Compare Mask High (DA_COMPARE_MASK_HI[0:3])Data Compare Mask High (D

Strany 659

8 AMD Geode™ LX Processors Data Book - List of Tables33234HTable 6-11. Data Only Command Buffer Structure . . . . . . . . . . . . . . . . . . . . . .

Strany 660

80 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.4 P2D Descriptor RegistersP2D descriptors are ordered P2D_BM, P2D_BMO, P2D_R

Strany 661

AMD Geode™ LX Processors Data Book 81GLIU Register Descriptions 33234H4.2.4.2 P2D Base Mask Offset Descriptor (P2D_BMO) See Table 4.1.3.1 "Memor

Strany 662

82 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.4.3 P2D Range Descriptor (P2D_R) See Table 4.1.3.1 "Memory Routing and

Strany 663

AMD Geode™ LX Processors Data Book 83GLIU Register Descriptions 33234H4.2.4.4 P2D Range Offset Descriptor (P2D_RO)See Table 4.1.3.1 "Memory Rout

Strany 664

84 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.4.5 P2D Swiss Cheese Descriptor (P2D_SC)See Table 4.1.3.1 "Memory Routi

Strany 665

AMD Geode™ LX Processors Data Book 85GLIU Register Descriptions 33234H4.2.5 SPARE MSRs (SPARE_MSR[0:9], A:F)MSR Address GLIU0: 10000040h-1000004FhGLI

Strany 666

86 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H4.2.6 I/O DescriptorsI/O descriptors are ordered IOD_BM, IOD_SC. For example if

Strany 667

AMD Geode™ LX Processors Data Book 87GLIU Register Descriptions 33234H4.2.6.2 IOD Swiss Cheese Descriptors (IOD_SC)See Table 4.1.3.1 "Memory Rou

Strany 668 - × M.WI 2/11

88 AMD Geode™ LX Processors Data Book GLIU Register Descriptions33234H

Strany 669

AMD Geode™ LX Processors Data Book 895CPU Core 33234H5.0CPU CoreThis section describes the internal operations of theAMD Geode™ LX processor’s CPU Co

Strany 670

AMD Geode™ LX Processors Data Book 9List of Tables33234HTable 6-66. Panel Output Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . .

Strany 671

90 AMD Geode™ LX Processors Data Book CPU Core33234H5.2 Instruction Set OverviewThe CPU Core instruction set can be divided into ninetypes of operatio

Strany 672

AMD Geode™ LX Processors Data Book 91CPU Core 33234H5.3 Application Register SetThe Application Register Set consists of the registers mostoften used

Strany 673

92 AMD Geode™ LX Processors Data Book CPU Core33234H5.3.1 General Purpose RegistersThe General Purpose registers are divided into four dataregisters,

Strany 674

AMD Geode™ LX Processors Data Book 93CPU Core 33234H5.3.4 EFLAGS RegisterThe EFLAGS register contains status information and con-trols certain operat

Strany 675 - 9.0Package Specifications

94 AMD Geode™ LX Processors Data Book CPU Core33234H5.4 System Register SetThe System Register Set, shown in Table 5-5, consists ofregisters not gener

Strany 676 - Package Specifications

AMD Geode™ LX Processors Data Book 95CPU Core 33234H5.4.1 Control RegistersA map of the Control registers (CR0, CR1, CR2, CR3, andCR4) is shown in Ta

Strany 677 - A.1 Order Information

96 AMD Geode™ LX Processors Data Book CPU Core33234HTable 5-7. CR4 Bit Descriptions Bit Name Description31:9 RSVD Reserved. Set to 0 (always returns 0

Strany 678

AMD Geode™ LX Processors Data Book 97CPU Core 33234H30 CD Cache Disable/Not Write-Through (Snoop). Cache behavior is based on the CR0 CD and NW bits.

Strany 679 - Table A-2. Revision History

98 AMD Geode™ LX Processors Data Book CPU Core33234HTable 5-11. Effects of Various Combinations of EM, TS, and MP BitsCR0[3:1] Instruction TypeTS EM M

Strany 680

AMD Geode™ LX Processors Data Book 99CPU Core Register Descriptions 33234H5.5 CPU Core Register DescriptionsAll CPU Core registers are Model Specific

Komentáře k této Příručce

Žádné komentáře