AMD K5 Uživatelský manuál stáhnout pdf (Strana 18)

AMD-K5 Processor Data Sheet 18522F/0—Jan1997

PRELIMINARY INFORMATION

cessor’s high performance. In addition to indicating where the

x86 instruction begins and ends, the predecode information

identifies the position of the opcode and the number of simple

RISC-like operations (ROPs) the individual x86 instruction

requires for later translation.

After the x86 instructions are predecoded, they are loaded into

the instruction cache. When accessed from the instruction

cache, the speculative instructions (x86 instructions from a pre-

dicted branch stream) are pushed into the byte queue and

await further decoding. The byte queue not only contains the

x86 instructions but also the associated predecode tags that

mark each instruction’s position and operation type.

4.6 Cache Architecture

Much of the AMD-K5 processor’s performance advantage can

be credited to the processor’s instruction cache architecture

and its ability to feed the processor core. Using separate

instruction and data caches eliminates the internal conflicts

over simultaneous instruction cache access and x86 loads and

stores. The processor’s 16-Kbyte instruction cache is dual-

tagged, avoiding the linear-to-physical address translation

required to access every entry and allowing faster cache

access. In addition, the processor maintains a separate set of

physical instruction tags for snooping and aliasing, and

through a special protocol, prevents flushing the cache even

during Translation Lookaside Buffer (TLB) flushes or context

switches.

The processor’s instruction cache implements a four-way set-

associative structure for maximum cache performance in a

given size and maintains branch prediction information with

every cache line.

The 8-Kbyte data cache allows two cache lines of data to be

accessed simultaneously in a single clock cycle, as long as sepa-

rate banks within the data cache are accessed. Supporting two

accesses per clock enables the data cache to overcome the

load/store bottlenecks inherent in the x86 architecture.

The AMD-K5 processor’s data cache uses a modified, exclusive,

shared, invalid (MESI) protocol to maintain data coherency

with other caches in the system and to ensure that a read from

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AMD K5 Uživatelský manuál Strana 18