AMD K5 Uživatelský manuál stáhnout pdf (Strana 57)

18522F/0—Jan1997 AMD-K5 Processor Data Sheet

PRELIMINARY INFORMATION

Pipelining The following pipeline cycles are supported by AMD-K5 pro-

cessors model 1 and model 2 with stepping level of 4 and

above:

■ Cacheable instruction cache cycle into a cacheable instruc-

tion cache cycle

■ Cacheable instruction cache cycle into a cacheable data

cache cycle

■ Cacheable instruction cache cycle into a non-cacheable

data cache cycle (could be I/O)

■ Cacheable instruction cache cycle into a non-cacheable

instruction cache cycle

■ Non-cacheable instruction cache cycle into a cacheable data

cache cycle

■ Non-cacheable instruction cache cycle into a non-cacheable

data cache cycle

■ Cacheable data cache cycle into a cacheable instruction

cache cycle

■ Cacheable data cache cycle into a non-cacheable instruc-

tion cache cycle

■ Non-cacheable data cache cycle into a cacheable instruction

cache cycle

■ Non-cacheable data cache cycle into a non-cacheable

instruction cache cycle

■ Write cycle (could be I/O) into a write cycle (could be I/O)

■ Write cycle (could be I/O) into a cacheable instruction

cache cycle

■ Write cycle (could be I/O) into a non-cacheable instruction

cache cycle

■ Write cycle (could be I/O) into a cacheable data cache cycle

■ Write cycle (could be I/O) into a non-cacheable data cache

cycle

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 99 100

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AMD K5 Uživatelský manuál Strana 57